Lab 10 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

Any advic e can that be bec aus e of gate delay s

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Unformatted text preview: Any advic e? Can that be bec aus e of gate delay s ? Volodymyr Kindratenko says: Oc t 28 You lik ely need a debounc ing c irc uit. Xuanyao Zhang says: Oc t 29 Are we required to manage to pre-s et it to 111, s inc e there is no s uc h func tion on 74175 Volodymyr Kindratenko says: No. Oc t 29 Geun Young Kim says: Oc t 29 It s eems that 2 NAND gates are required for the debounc ing c irc uit. However, me and my partner have us ed up all the gates available in the Quadruple 2-input Pos itive-NAND Gates , and only have a Dual 4-input NAND gates available. Could we mak e a debonc ing c irc uit out of the 4-input NAND gate? Volodymyr Kindratenko says: Oc t 29 Sure. Jus t c onnec t pairs of their inputs together. Matthew Lee says: Oc t 30 Can y ou c onnec t all s witc hes to the s ame debounc ing c irc uit or does eac h s witc h need a s eparate one? Volodymyr Kindratenko says: You c an reus e a debounc er, but this will be logis tic ally diffic ult. Oc t 31...
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This document was uploaded on 03/22/2014.

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