Lab 10 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

Lab 10 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

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Lab 10 - FL13 Lab 10 assignment is to be shown to a TA in office hours on Monday, Tuesday, Wednesday, or Thursday. You need to show both a working circuit and the schematic labeled with pins used for each gate. Due to unforeseen difficulties, the vending machine hardware is not available this semester, the TAs will use switches to demonstrate the correct functionality of your circuit. Please do not leave it all to the last day (Thursday)! We will not have enough space and time to accommodate all students in one day. Therefore, to encourage you to do the lab earlier, we will give 1 bonus point (~4% of the lab grade) for turning in the assignment on Monday, or Tuesday and 0.5 bonus points (~2% of the lab grade) for turning in the assignment on Wednesday . Once you are done with the Lab, return your prototyping board kit to the electronics shop, unless you are working on a James Scholar project using the kit. In this case, you can keep it until the end of semester. If you need to use test and measurement equipment, you can do so on Tuesday and Wednesday 9am-10:30am in 146 Everitt (ECE 110 lab). There will be a TA available for help. Sequential logic implementation In this lab, we will complete the implementation of the vending machine example on your protoboard. In Lab 8, you implemented a combinational logic circuit that encoded the states of a finite state machine into two output signals "Accept coin ( A )" and "dispense Product ( P )." In Lab 9, you designed the finite state machine in Mentor Graphics. In this lab, you will work on the protoboard implementation of that state machine. You will test it with the sensor/actuator device described below. Implementing the State Machine on the Protoboard Redesign your next-state logic design from Lab 9 so that it uses only NAND, NOR, and NOT gates (See Lab 8 for datasheets). To prototype your flip-flops, we recommend that you use either the 7474 DIP or the 74175 DIP. The top data sheet shows the pin layout for the 7474 DIP which has two distinct positive-edge-triggered D flip-flops. Note the behaviors of the PRESET and CLEAR. The lower data sheet shows the pin layout for the 74175 DIP which has four positive-edge-triggered D flip-flops which share common CLEAR and CLOCK signals. When the CLEAR signal is 1 it asynchronously resets all of the flip-flops to store 0. Also note that the scan of the data sheet is a little poor and some of the complement symbols have been lost.
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Implement your state machine and connect it to your circuit from Lab 8 that generates your outputs A and P.
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