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datas heets ).
To prototy pe y our flip-flops , we rec ommend that y ou us e either the 7474 DIP or the 74175 DIP. The top data s heet s hows the
pin lay out for the 7474 DIP whic h has two dis tinc t pos itive-edge-triggered D flip-flops . Note the behaviors of the PRESET and
CLEAR. The lower data s heet s hows the pin lay out for the 74175 DIP whic h has four pos itive-edge-triggered D flip-flops whic h
s hare c ommon CLEAR and CLOCK s ignals . W hen the CLEAR s ignal is 1 it as y nc hronous ly res ets all of the flip-flops to
s tore 0. Als o note that the s c an of the data s heet is a little poor and s ome of the c omplement s y mbols have been los t. Implement y our s tate mac hine and c onnec t it to y our c irc uit from Lab 8 that generates y our outputs A and P. Do not forge t
to de ta ch your sw itch inputs first to your La b 8 circuit, le st the y drive a ga inst the sta te outputs a nd burn out your
Connec t y our c urrent s tate outputs , S2, S1, and S0, as well as y our nex t s tates , S2+ , S1+ , and S0+ , and A and P to LEDs
s o that y ou (and the TAs ) c an eas ily c hec k to s ee whether y our c irc uit implements the c orrec t s tate trans iti...
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- Fall '14