Lab 9 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

Lab 9 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

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Lab 9 - FL13 Lab 9 assignment is due on Friday, October 25 Monday, October 28 in class. This lab is to be done in the EWS computer lab (DCL 440, DCL 520, etc.). Working on it remotely is not advisable as there are numerous technical difficulties in getting the software to work properly with remote access. Plan your time accordingly. Read Prof. Lumetta's lecture notes set 3.3: Design of the Finite State Machine for the Lab for a detailed description of the FSM used in this lab. The notes also provide K-maps for next-state logic you need to implement in this lab. Sequential logic design In this lab, we will complete the design of the vending machine example in Mentor Graphics. In Lab 7, you designed a combinational logic circuit that encoded the states of a finite state machine into two output signals "Accept coin ( A )" and "dispense Product ( P )." In this lab, you will design a circuit implementation of the state machine developed in Lecture 22 and shown below. Here each state is encoded using three state variables ( S2S1S0 ) and the outputs are encoded using the output variables ( AP ). For example, in the "Reject Q" state, S2S1S0 = 110 and AP = 00. The state transitions are labeled with the variable T . T = 1 when a quarter has been inserted and T = 0 when a dime has been inserted. This state machine is also driven by a clock that indicates when a coin has been inserted. Implementing the State Machine in Mentor Graphics Design the next-state logic for your circuit on pencil and paper using the techniques you have learned in class. Design your circuit so that it uses positive-edge-triggered D flip-flops. Open Mentor Graphics and create a new block diagram schematic like you did for labs 4 and 6. To add a positive-edge-triggered D flip-flop, go to the "Add" menu and select moduleware. In the component browser, open the "registers" library and drag and drop the "D FF" component onto your circuit diagram. You should notice that the D flip- flop (picture below) has many more inputs than we normally use ( load , set , and reset ( rst )). These three inputs are asynchronous inputs and they alter the behavior of the D flip-flop. These asynchronous inputs allow us to set the initial state of our circuit which is handy if we just want to simulate a specific state transition.
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When the rst input is 1, the D flip-flop stores a 0 regardless of the values of any other inputs. When is 0 and set is 1, the D flip-flop stores a 1 regardless of the values of any other inputs. When and set are 0, the load signal controls whether the D flip-flop can update its state in response to the D and clock inputs. When load is 0, the flip-flop cannot change state. When load is 1, the flip-flop will store the value of $d$ on the next positive-edge of the clock. The clk input is the clock. d input is the data input for the flip-flop.
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Lab 9 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

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