Lab 15 - FL13
This lab is to be done in the EWS computer lab (DCL 440, DCL 520, etc.). Working on it remotely is not advisable as there
are numerous technical difficulties in getting the software to work properly with remote access. Plan your time accordingly.
This lab is due on Wednesday, December 11, in lecture.
Overview and objectives
During this lab, you will learn a little bit about how we implement the LC-3 architecture in VHDL. First, you will debug a buggy
version of the LC-3 architecture. Then, you will add a new instruction NEG to the LC-3 architecture. Finally, you will write a short
program to demonstrate that you have correctly debugged the architecture and that your new instruction works correctly. Due to the
complexity of the LC-3 architecture, this lab may take a little longer than previous labs, so it may help to start early!
In this section, you will download the LC-3 library
(we apologize for the odd name, but this lab used to be lab7 in a
previous course and it is very difficult to change the name of a library).
Create a "lab7" directory in your ECE 198 directory
Download the LC-3 libary to your lab7 directory (lab7.zip
Unpack the library with the command
to create a "lab7_lib" directory
If necessary, move your lab7_lib directory so that its path is /home/[YOUR_NETID]/[YOUR ECE 198
Open HDL designer and create a new project called "lab7". Set the path of the project to /home/[YOUR_NETID]/[YOUR ECE
198 DIRECTORY]/lab7/ and set the library to use "lab7_lib". Make sure that you include the last /.
Click next twice and then choose "Open the Project" and click Finish.
When you create this project, it should become populated with all the files you need. If not, delete the lab7.hdp file in your lab7
folder and try the directions above again.
Debugging the LC-3: Repairing a Broken Microinstruction
In this part of the lab, we will show you how to navigate parts of the LC-3 architecture and show you how to modify its control words
(microinstructions). We have written a program in the LC-3 architecture that executes the instruction
ADD R0, R6, 5.
Since R6 is
first loaded with the value x300D before we execute the
ADD R0, R6, 5
instruction, this instruction should load R0 with the value
x3012. As you will see, this instruction contains a bug.
Starting the simulation
In Design Manager window you should see several components in the lab7_lib library that compose the LC-3 architecture. Locate
the CPU component. Feel free to open the component and other components to explore if you are curious, but we will focus on
simulating the CPU as a whole.
Select the CPU component
Start the simulator. If ModelSim won't start or if you get errors after you open ModelSim, please scroll to the bottom of the
instructions to the Troubleshooting section.