Lab 6 - FL13 - ECE 198 JL - University of Illinois - Engineering Wiki

Your lab k it has an abundanc e of nand and nor gates

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Unformatted text preview: tor-trans is tor logic (TTL) c hips . Your lab k it has an abundanc e of NAND and NOR gates , but no AND and OR gates . Remember that it is eas ier to implement NAND with c ertain tec hnologies s uc h as CMOS and TTL. Let's begin with a brief tutorial on TTL c hips . A TTL c hip is als o c alled a dual-inline pac k age (DIP). Eac h DIP has a s mall notc h whic h indic ates the "top" of the DIP. All pins on a DIP are numbered s o that we c an matc h the phy s ic al DIP with the s pec ific ation. The pin immediately to the left of the notc h is c alled Pin 1. The remaining pins are numbered with inc reas ing numbers in a c ounter c loc k wis e direc tion around the DIP. Eac h DIP has a + 5V power pin and a ground pin. Thes e pins provide power and ground to eac h gate or c omponent on the c hip and are ty pic ally loc ated in the c orners of the DIP. 1. Dis c onnec t battery from y our protoboard. 2. Find a 7400 (or 74LS00) c hip in y our c hip k it. Look for the numbers printed on the top of the DIP. The 7400 TTL c hip has four (or "quad") two-input NAND gates eac h with two inputs and one output as s hown in the s pec ific ation below. 3. Find the "top" of the c hip by finding the s mall groove on one s ide of the DIP 4. Ins ert the 7400 DIP into a terminal s trip near y our debugging s tation and s o that it bridges a c enter c hannel. W e s trongly rec ommend that y ou ins ert all of y our c hips s o that the top notc h is pointing towards the power and ground jac k s . Cons is tenc y in y our c hip orientation will limit the pos s ibility for errors and will eas e debugging 5. Connec t Pin 14 to a nearby power bus and c onnec t pin 7 to a nearby ground bus . W e rec ommend us ing the s hortes t wires pos s ible, and us ing red for power and blac k for ground, to again help with debugging. 6. W e c an c hoos e any of the four NAND gates on the DIP, but lets c onnec t the NAND gate that us es pins 1, 2, and 3. W hen y ou build y our own c irc uits , we s trongly rec ommend that y ou draw a c irc uit diagram lik e the one below that tells y ou whic h DI...
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This document was uploaded on 03/22/2014.

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