ECE3060 testIIsolution

ECE3060 testIIsolution - ECE 3060 Advanced Digital Design...

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Unformatted text preview: ECE 3060 Advanced Digital Design and VLSI Test l Thursday, April 19, 2007 This exam is closed book closed notes. Calculators are permitted. You may have two sheets of hand written notes. There are Four questions. Do read them over before you start to work. If you need to make any assumptions, state them. The meaning of each question should be clear, but if something does not make any sense to you, please ask for clarification. Please continue problems on the hack of the previous page. Good Luck! Name (Please print) This exam will be conducted according to the Georgia Tech Honor Code. I pledge to neither give nor receive unauthorized assistance on this exam and to abide by all provisions of the Honor Code. Signed 1. (15) Logical effort of a gate. a) (10) Calculate the lagical effort 99.0133 of an A0133 gate as a function of y. Show the proto- type gate complete with transistor sizes. VW EtZY. 5W gt’X m) 2 {mime w n% 52.3%; 47' 3 WW1“ b) (5) Assuming that y=2, calculate the logical efforfls) gems] of an OAIBI gate. Show the pro- totype gate complete with transistor sixes. ! 33 Y? (x f it: I F 1:! (lit-{34%) I) AM + {>6 F £62»? +2“; F5) (54%“??? 2. (25) Logical effort calculations a) (15) Minimize the delay from fhe circuil inpul lo 2, assuming ihai' ’rhe delay lo all three loads should be abou’r the same, and y=2. Give ‘rhe delay to drive 2, the maximum delay to any load, and ’rhe sizing of fhe gale iha’r drives 72 assuming Wmm = 32 X Pm Wm y'all/41.5?) ML; m imp/Jr floated mm N022. ai— iizgy [WW 33w « brawl/1W (4 2.25, 4M}. % if - a 1/1, H. “i Arm/Rx [Moo/l 34/{T’) b) (10)Design an implementation of F =ab+ac+bc which drives a load of 20061”, wifh minimum delay. Assume thm‘ y=2, and that the maximum permissible load on ’rhe inpu’rs is 4cm . Draw your circuit and estimate the delay. You do NOT ned to size your circuit 5m we W' W is We) MAJ) [look as» Salum win, AIM/g) 2. zmwfi. m : A 26pm” C” $1 200 Claw": 4‘05 CFfiT >-l>o f l; M W 2,2659%) as». flu 5; W 111.!be 1,404 l Jifgi «Q fl/fl'zl/l) ‘2 .7 593 Aim/L. Alibi/z) 43L m,;7 9;? (“1297‘ Cafsz ' fit: 36?) 33! {jihc'g we Pa‘!’ {‘11: JIM 6+ 7%“ “77°7L A 3 G=%) A ‘ FSéBH : g 300 ~‘-‘ 7/! N = by“ F c 54 Wm ol/mzu N3“! ’i’b “ll/0153715 Matt/6:1. (WM 14: bVlVW-tC/S +0 mail/[7347!" '37: m2 Cit/Cow'f’ W : TM 415': F7“ : 7llhz‘3,o‘t 19—; (9,344 c '27-: “Aalwwu cad/‘0‘? A“; A Luca,“ {4%, 939$,» uh W 41100“ WEEK; (991A “like Ji > .1 mpg} "mm #5100! w 872, , TLQ femwaiq 0+ m enhml’vmu ls Somdw h 3vka 3. (30) Minimization a) (15) Perform Branch and Bound on the given matrix. Give the selection vector x returned by all branches of the algorithm. FKVYQ’ +3: E’YLILJ" Hg.“ L (damn 2, ;\ esswfigg (Shake a} «om/Q ft: moi/4,1,) 2, (ohm! 1:. domw {sémke m) 5 Candi/In» n Y t) domgnM (54"ny Mo reptild‘i'fi’l p§$‘i ' ‘ {bfwiifigLu/iracaiwn 3 2:4 (“UN EyM’Vlzfl “4% X73(°“000) 751 176 am} PI: ("j/M ' I ‘1'. COiVWin ‘l M 4/! (:0’ Chasm/(94 Cm‘una L? W Vti'vrnrgfll‘ [011190] ~ Rana“; Ceiw'm 3 {ram Hm 50b H34. («Li Ei‘euiflzw “(’14 r ‘ 77am w>XT: [0106003 mil A: D! #3 ‘il"‘ 4. are have; fixfmhvf . g c OQLUMn 1+ M (Sf/(N loam 5mg «H rows) i’e’lf‘w‘h 327-:[0101917 fin“, the flu: mm 07“ fig, few”? 9 W611 ’HLL Who/m 57° J4“ 1%th firm m fflrfil' rem/5% Wf (ya/{I f‘gy‘j'pyiv nyvEOHI 3007 fie/Vm/(j) b) (lO)Find an OBDD represenfing the function F=Zbd+abc+abc . Use fhe variable order abcd. c) (5) WM? is the expansion of the implicanf abc in ihe a dimension? Using ONLY fhe graph from b), is ihis expansion confained in the func’rion F? 6" {)C ‘2“ 5t A Witoi.‘ 2526.5 LC . m CO’I‘F’w/I’U/ FLC i5 (WW-Vch 6 9.2.2 Ii“! Fin“: 1) {M i) Lafikrael 1" F 4. (30) Technology Mapping a) (15) Consider a technology library (wifh area cos’rs) containing a NANDZ (cos’r=3), NORZ (cosf=4) INV (cosl=l), and OAIZI (cos+=2). Using fhe base function symbols 0 For a NANDZ, O For an inverfer, and a hushed circle for inpu’rs, draw the pattern frees for the library. ’NKNQZ ' @ W ' COS :9? _ cave- 2 NO? 1 aoaw INV b) (15) Using the circuit shown, draw the subject tree using the symbols From part a), and per- form the dynamic programming technology mapping algorithm as presented in class. You must show each step of the algorithm. A correct answer with no (correct) work will receive no credit. ...
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ECE3060 testIIsolution - ECE 3060 Advanced Digital Design...

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