004 spring 2009 1 of 4 quiz 4 problem 2 7 points cache

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Unformatted text preview: -e n tr a n c e : Y E S … N O 6.004 Spring 2009 - 1 of 4 - Quiz #4 Problem 2 (7 points): Cache Management Four otherwise identical Beta systems have slightly different cache configurations. Each cache has a total of 8 lines each caching a single 32-bit data word, and caches both instruction and data fetches. However, the caches differ in their associativity as follows: Cache C1: Direct mapped, 8-word cache. Cache C2: 2-way set associative (4 sets of 2 lines), LRU replacement. Cache C3: Fully associative, LRU replacement. Your task is to answer questions about the performance, measured by hit ratio, of these cache designs on the following tiny benchmarks. Note that each benchmark involves instruction fetches starting at location 0 and data accesses in the neighborhood of location 1024 (= 210). .=0 || Benchmark B0 CMOVE(100, R1) LOOP: LD(R31, 1024, R0) SUBC(R1, 1, R1) BNE(R1, LOOP) HALT() .=0 || Benchmark B2 CMOVE(100, R1) LOOP: LD(R31, 1024+4, R0) LD(R31, 1024+8, R0) SUBC(R1, 1, R1) BNE(R1, LOOP) HALT() .=0 || Benchmark B1 CMOVE(100, R1) LOOP: LD(R31, 1024+4, R0) SUBC(R1, 1, R1) BNE(R1...
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This document was uploaded on 03/17/2014 for the course ELECTRICAL 6.004 at MIT.

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