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Unformatted text preview: ock size, 214 words total data. Cache
access (hit) time: 5 ns
MMU design: single-level PageMap, 230-byte virtual address space, 228-byte physical address space, page size 214 bytes. MMU access (translation) time: 5ns. RAM (main memory) access (read or write) time: 40 ns.
Assume that other times (e.g. gate delays) are insignificant compared to memory access times.
Note that all memory accesses — including LDs and STs as well as instruction fetches — are
made via the above path.
(A) (1 point) Assume that each page map entry includes Resident and Dirty bits as well as a
physical page number. What is the total size, in bits, of the pagemap storage?
20 16 2 = 16 × 2
Total page map size (bits): ____________________________________
(B) (2 points) What is the memory access time for a cache hit? A miss? 50
Access times on HIT: _________ns; on MISS: ________ns
(C) (1 point) Assuming a 90% hit rate, what is the expected average access time? 14
Average access time for 90% hit rate: ________ns
(D) (2 points) Which, if any, of the following operations must the operating sys...
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This document was uploaded on 03/17/2014 for the course ELECTRICAL 6.004 at MIT.
- Spring '09
- Electrical Engineering