{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

quiz4 - M A S S A C H U S E T T S I N S T I T U T E O F T E...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
M A S S A C H U S E T T S I N S T I T U T E O F T E C H N O L O G Y DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE 6.004 Computation Structures Spring 2009 Quiz #4: April 24, 2009 Name Solutions Athena login name Score Avg: 16.5 NOTE: Reference material appears on the backs of quiz pages. Problem 1 (7 points): Quickies and Trickies (A) (1 point) A Beta processor has an interrupt handler invoked by a periodic 60Hz clock. The handler simply inspects the high-order bit of the XP register to see if it is a 1 or 0. Give your best estimate of the fraction of the time it finds a 0. Circle best answer: 0% … 50% … 100% (B) (2 points) An application program that stores data in the XP register might fail due to (circle YES or NO for each): Interrupt handler returns to wrong location: YES … NO Application data in XP changes unexpectedly: YES … NO Interrupt executes wrong handler: YES … NO (C) (2 points) Decrementing the saved PC of an interrupted program often indicates (circle YES or NO for each): re-entrant interrupts: YES … NO a cache miss: YES … NO “busy waiting”: YES … NO a programming error: YES … NO (D) (2 points) Use of a Translation Lookaside Buffer (circle YES or NO for each): decreases cache hit rate: YES … NO decreases average address translation time: YES … NO prevents handler re-entrance: YES … NO 6.004 Spring 2009 - 1 of 4 - Quiz #4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Problem 2 (7 points): Cache Management Four otherwise identical Beta systems have slightly different cache configurations. Each cache
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}