ph_ch4_P1 - CoE3DR4 Computer Organization Chapter 4...

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CoE3DR4 Computer Organization Chapter 4
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Introduction Performance of a machine is determined by three factors: instruction count, clock cycle time, and clock cycles per instruction (CPI) The complier and ISA determine the instruction count required for a given program Clock cycle time and number of CPI are determined by processor implementation In this chapter we construct the datapath and control unit for two different implementation of MIPS instruction set
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Introduction The datapath is the interconnection of the components that make up the processor. The datapath must provide connections for moving bits between memory, registers and the ALU. The control is a collection of signals that enable/disable the inputs/outputs of the various components. You can think of the control as the brain, and the datapath as the body. the datapath does only what the brain tells it to do. We will implement a subset of core MIPS : lw and sw add, sub, and, or and slt beq and j Effect of different implementation choices on clock rate and CPI
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Implementation overview Two identical first step for every instruction 1. Send PC to memory and fetch the instruction from that location 2. Read one or two registers, selected by fields of instruction opcode (one register for lw, two for most of the other instructions) Perform the actions to accomplish the instruction Actions are largely the same, independent of exact opcode Holds for each instruction class: memory reference, arithmetic-logic, and branch
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Implementation overview All instruction classes (except jump) use ALU after reading registers Memory reference instructions use ALU for address calculations Arithmetic-logic instructions use ALU for operation execution Branch instructions use ALU for comparison Post-ALU execution of instructions Memory-reference instruction needs to access memory for load or store Arithmetic-logic instruction must write data to a register Branch instruction needs to change the PC for next instruction address based on comparison Figure 4.1 High level view of a MIPS implementation
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Implementation overview
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Implementation overview Two important aspects of instruction execution are missing: 1. Data going to a particular unit is coming from two sources We have to use multiplexer Control lines of the multiplexers are set based on information taken from the instruction being executed 2. Several of the units must be controlled depending on the type of instruction Example: data memory must read on a load and write on a store Example: ALU must perform one of several operations These operations are directed by control lines that are set on the basis of various fields in the instruction
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Implementation overview
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Implementation overview A control unit that has the instructions as an input is used to determine how to set the control lines for the functional units and two of the multiplexers
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  • Spring '12
  • Central processing unit

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