ph_ch4p2 - The Laundry Analogy Non-pipelined approach 1 2 3...

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The Laundry Analogy Non-pipelined approach: 1. run 1 load of clothes through washer 2. run load through dryer 3. fold the clothes 4. put the clothes away Two loads? Start all over.
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Pipelined Laundry While the first load is drying, put the second load in the washing machine. When the first load is being folded and the second load is in the dryer, put the third load in the washing machine.
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Figure 6.1
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Laundry Performance For 4 loads: non-pipelined approach takes 16 units of time. pipelined approach takes 7 units of time. For 816 loads: non-pipelined approach takes 3264 units of time. pipelined approach takes 819 units of time.
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Execution Time vs. Throughput It still takes the same amount of time to get your favorite pair of socks clean, pipelining won’t help. However, the total time spent away from studying for COE3DR4 is reduced
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Pipelining We can overlap the execution of multiple instructions. At any time, there are multiple instructions being executed – each in a different stage.
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Instruction Pipelining First we need to break instruction execution into stages: 1. Instruction Fetch 2. Instruction Decode/ Register Fetch 3. ALU Operation 4. Data Memory access 5. Write result into register
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Operation Timings Some estimated timings for each of the stages: Register Write 100ps Register Read 100ps ALU Operation 200ps Memory access 200ps
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Operation Timings Instruction Instruction Register ALU Data Register Total class fetch read operation memory write Load word 200 100 200 200 100 800ps Store word 200 100 200 200 700ps R type 200 100 200 100 600ps Branch 200 100 200 500ps
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Comparison
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MIPS and Pipelining MIPS design features that make pipelining easy include: single length instruction (always 1 word) Makes it easier to fetch instructions in the first pipeline stage and decode them in the second one relatively few instruction formats Second stage can begin reading register file at the same time as the hardware is determining type of the instruction Memory operands only appear in load/store instruction set We can calculate memory address and access memory in the following stage operands must be aligned in memory (a single data transfer instruction requires a single memory operation). We need not worry about a single data transfer instruction requiring two data memory access
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Task-time diagram IF: instruction fetch (box representing instruction memory) ID: instruction decode/register file read stage (box representing register file) EX: execution stage (drawing represents the ALU) MEM: memory access stage (box representing data memory) WB: write back stage (drawing represents the register file) Shading means the element is used Shading of left half means writing and shading of right half means reading
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Pipeline Hazard Something happens that means the next instruction cannot execute in the following clock cycle.
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  • Spring '12
  • Central processing unit, Instruction pipeline, Instruction processing, data hazard

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