G capacitor option mim 2 level poly channel implant

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Unformatted text preview: devices © 2006 A. M. Niknejad and B. Boser 9 Process Options • Available for many processes • Add features to “baseline process” • E.g. – – – – – – Capacitor option (MIM, 2 level poly, channel implant) Low VTH devices “High voltage” devices (3.3V) EEPROM Silicide stop option … EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 10 Silicide Technology • Implants used to lower resistance of source/drain and polysilicon. • Titanium Silicide (TiSi2) is widely used salicide (self-aligned silicide), has low resistivity (13-17 mΩ-cm) with melting point of 1540˚C. Another widely used silicide is CoSi2. • Platinum Silicide (PtSi) is a highly reliable contact metallization between the silicon substrate and the metal layers (Al). EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 11 Silicide Block Option Layer N+ poly P+ poly N+ diffusion P+ diffusion N-well R/ [Ω/ ] 100 180 50 100 1000 TC [ppm/oC] @ T = 25 oC -800 200 1500 1600 -1500 VC [ppm/V] BC [ppm/V] 50 50 500 500 20,000 50 50 -500 -500 30,000 • Non-silicided layers have significantly larger sheet resistance • Resistor nonidealities: – Temperature coefficient: R = f(T) – Voltage coefficient: R = f(V) EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 12 Resistor Example Goal: R = 100 kΩ, TC = 1/R x dR/dT = 0 Solution: combination of N+ and P+ poly resistors in series R = RN (1 + TCN ∆T ) + RP (1 + TCP ∆T ) = RN + RP + (RN TCN + RPTCP )∆T 1 2 3 144 44 44 2 3 R RN = R RP = R ⇒ 0 1 = 20kΩ = 200 squares TCN 1− TCP 1 = 80kΩ = 444.4 squares TCP 1− TCN EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 13 Voltage Coefficient - Example: Diffusion resistor + p substrate p diffusion n- well n+ diffusion V1 V2 Applied voltage modulates depletion width (cross-section of conductive channel) VB Well acts as a shield R V1 − V2 I V +V ≈ Ro 1 + TC (T − 25o ) + VC (V1 − V2 ) + BC 1 2 − VB 2 R= EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 14 Resistor Matching • Types of mismatch – Systematic (e....
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