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lect2 - EECS 240 Analog Integrated Circuits Lecture 2 CMOS...

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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 1 EECS 240 EECS 240 A A nalog Integrated Circuits nalog Integrated Circuits Lecture 2: CMOS Technology and Lecture 2: CMOS Technology and Passive Devices Passive Devices Ali M. Niknejad and Bernhard E. Boser © 2006 Department of Electrical Engineering and Computer Sciences
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 2 CMOS Technology CMOS Technology Why look at it (again)? Key issues : 1. Perspective Device dimensions Device performance metrics, e.g.: Current efficiency Speed Gain Noise 2. “Short-channel characteristics” Square-law model Models for circuit simulation Design
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 3 Today Today s Lecture s Lecture CMOS cross-section Passive devices – Resistors – Capacitors Next time: MOS transistor
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 4 CMOS Process CMOS Process EECS240 0.18 µ m 1P6M CMOS Minimum channel length: 0.18 µ m 1 level of polysilicon 6 levels of metal (Cu) 1.8V supply Other choices Shorter channel length (90 nm / 1V) Bipolar, SiGe HBT – SOI
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 5 Supply Voltage Supply Voltage 0 1 2 3 4 5 1 0.8 0.5 0.35 0.25 0.18 0.12 0.08 0.06 Feature Size [μm] Supply Voltage [V]
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 6 CMOS Cross Section CMOS Cross Section Metal Poly p - substrate n - well p + diffusion n + diffusion
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 7 Dimensions Dimensions 700m µ 6.5nm 0.35 µ m 1.2m µ 200nm Drawing is not to scale!
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 8 Devices Devices • Active – NMOS, PMOS – NPN, PNP – Diodes • Passive – Resistors – Capacitors – Inductors
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 9 Resistors Resistors No provisions in standard CMOS Resistors are bad for digital circuits Æ Minimized in standard CMOS Sheet resistance of available layers: Example : 100k poly resistor Æ 1 µ m wide by 20,000 µ m long 60 m / ± 5 / ± 5 / ± 1 k / ± Aluminum Polysilicon N+/P+ diffusion N-well Sheet resistance Layer
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 10 Process Options Process Options Available for many processes Add features to “baseline process” • E.g. Capacitor option (MIM, 2 level poly, channel implant) Low V TH devices “High voltage” devices (3.3V) – EEPROM Silicide stop option – …
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EECS 240 Lecture 2: CMOS - passive devices © 2006 A. M. Niknejad and B. Boser 11 Silicide Silicide Technology Technology Implants used to lower resistance of source/drain and polysilicon.
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