Lecture Notes_23-26_MOSFET_2014

The maximum gate voltage will also be scaled from vg

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Unformatted text preview: the saturation region at the Q- point shown (Quiescent). The figure plots ID as a function of VDS. By inspection VDD = IDRD + VDS. The load line is ID = (VDD – VDS)/RD , as shown. When a time- varying input signal vi is applied to the gate, a time- varying drain current is induced that in turn causes a time- varying drain- to- source voltage. A time- varying output signal is generated whose magnitude can be greater than that of the input signal. Thus, the circuit is a voltage amplifier. The figure of merit for an FET is transconductance, gm = dID/dVGS, which is in contrast to the usual conductance, such as drain conductance gD = dID/dVDS, From the equations for ID in Slides 16 and 17, we can calculate the transconductance in the non- saturation regime and the saturation regime. The unit for conductance is Siemen (S). We see that W and L are important device design parameters. In particular, the...
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