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Unformatted text preview: ame # out.
• Otherwise get frame # from page table in memory Page
Large page sizes
Small page sizes
Later with virtual memory, we’ll see other constraints
page size is always a power of 2 Paging
indirect address translation via page tables
more efficient use of memory – little fragmentation
downside: page table memory Break
Page Table Size
Page tables can get really large
32 bit address space (20 page, 12 offset)
page size of 4K (2^12)
1 million entries each of N bytes (if PTE is 4 bytes =>)
4 MB per process! (if we allocate full addr range)
That is a lot of contiguous memory to allocate – remember
the discussion of holes? Why are page tables contiguous?
Clearly, we will have greater flexibility if we can allocate
memory for the page table non-contiguously
How do we do this? Page it like any other (user) memory! Two
Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is divided into:
• a page number consisting of 20 bits
• a page offset consisting of 12 bits Since the page table is paged, the page number is further divided into:
• a 10-bit page number
• a 10-bit page offset Thus, a logical address is as follows:
page number page offset
pi p2 d 10 10 12 where pi is an index into the outer page table, and p2 is the displacement within the page
of the outer page table. Address
Address-translation scheme for a two-level 32-bit paging
p1 p2 d This contains the
logical page i of
page table and
frame in memory Hold several PTEs
p1 p2 Outer-page
table d page of page
table How big should the outer-page table be? Assume PTE=4 Multi
Multi-level Page Tables
How big should the outer-page table be?
Have we reduced the amount of memory required for paging? Page tables and
Process memory are
Multilevel Paging and Performance
Since each level is stored as a separate table in memory, mapping a
logical address to a physical one may take three or more memo...
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This document was uploaded on 04/02/2014.
- Summer '14
- Operating Systems