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Set up a page table to translate logical to physical addresses.
page i -> frame ?
Some internal fragmentation. Address
Address Translation Scheme
Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which
contains base address of each page in physical memory.
• Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit.
memory 0 text
BSS 511 user stack
kernel Page size (PS)
Frame size PS = 128 Address
Address Translation Architecture p (or vpn) =
log_addr % PS
phys_addr = frame table
not shown Simple
Simple Paging Example PS
PS = 128
log_addr = 130
vpn = log_addr/PS
d = log_addr % PS
phys_addr = PS*PT[vpn]+d A Simple Page Table
Each process/VAS has
its own page table.
Virtual addresses are
translated relative to
the current page table. process page table
PFN 1 PFN i In this example, each
VPN j maps to PFN j,
but in practice any
physical frame may be
used for any virtual page. PFN i
page #i offset user virtual address physical memory
page frames The page tables are
themselves stored in
memory; a protected
register holds a pointer to
the current page table. Page
Page and Address Sizes
Suppose logical address consists of:
20 bits for the page number
12 bits for the offset
How big is a virtual address?
What is the size of a page?
How big is the virtual address space?
How many entries are in the page table?
How much memory does the page table take up? Implementation
Implementation of Page Table
Page table (for each process) is kept in main memory.
Page-table base register (PTBR) points to the current page table.
Page-table length register (PRLR) indicates size of the page table.
In this scheme every data/instruction access requires two memory
accesses. One for the page table and one for the data/instruction.
The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative registers or
translation look-aside buffers (TLBs) Translation
Translation Lookaside Buffer (TLB)
Associative registers – parallel search Page # 0 Frame # 1 Address translation (A´, A´´)
• If A´ is in associative register, get fr...
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This document was uploaded on 04/02/2014.
- Summer '14
- Operating Systems