For writes issue them in order but if they go to

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Unformatted text preview: r. [How can we guarantee that a CPU reads another CPU’s writes in issue order? One way would be to slow everything down to a crawl: issue one write, wait for it to complete, before issuing the next write. Or put all data on the same server. We’ll see that caching allows us to consider some other implementations.] If you program in a high level language, the compiler might think each CPU operates independently, on its own local memory, and therefore it is free to say that since v0 and done0 have no data dependency, so that they can be reordered by the compiler. Problem B: CPU2 may see CPU1's writes before CPU0's writes i.e. CPU2 and CPU1 disagree on order of CPU0 and CPU1 writes (what if we implement cache coherence by sending the update to every node? Would your RPC design have this problem?) Thus, the behavior of a program can depend on the “memory model” – that is, what behavior can we expect from memory. Complexity of the memory model arises out of the desire to do things quickl...
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This document was uploaded on 04/04/2014.

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