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Unformatted text preview: -‐only, invalid, for each client x each memory object. Constraints: owned by at most one client (at a time) Read-‐only at any client => not owned by any client What causes transition for each state? Illustrate original example, using write back cache coherence. CPU0: v0 = f0(); done0 = true; CPU1: while(done0 == false) ; v1 = f1(v0); done1 = true; CPU2: while(done1 == false) ; v2 = f2(v0, v1); What cache misses occur, what data is transferred? Initially, nothing cached. Eventually, v1 and v2 gets the right value. Efficiency of write back versus write through: write back is more efficient if there are repeated writes to the same location; in this example there are no repeated writes. So would write through do the same thing as write back, or does write back have to do more work if there are no repeated writes? We’ve been assuming that each variable is independently cached. What happens if some variables are used differently, but are in the same unit of sharing (cache line, distributed object, file)? That is called:...
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This document was uploaded on 04/04/2014.
- Spring '14