So cpu3 and cpu4 can see either cpu1s write or cpu2s

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Unformatted text preview: ions. But it is causally consistent! So no advantage to doing causal ordering? In most cases, it does what you want. For example, the code we started with, should work correctly with causal ordered memory. Other forms of weak memory consistency: provide sequential consistency only across explicit synchronization operations. For example, the compiler could reorder memory operations, except that if the system called an explicit “barrier” operation across all the CPUs, then the memory operations before the barrier would need to complete before any of the memory operations after the barrier. If we had a barrier after “done” in the example, program would work correctly. Another version of this: group operations that need to be sequentially consistent with each other; allow operations in other groups to be done in any order with respect to each other. Finally: in the limit, eventual consistency: a read returns a recent version of the data, but not necessarily the most recent version, or one that is consistent wit...
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This document was uploaded on 04/04/2014.

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