Unformatted text preview: cy allows for certain types of compiler and hardware optimizations, especially when there are multiple physical memories. Is this optimization ok in a serializable system? A linearizable one? Write buffering – to buffer or queue a write at the client, and then continue to execute the next instruction/operation while the write is being performed in the background. Is there an implementation that is sequentially consistent, but not linearizable? Simple case: one processor Store 1 at x Add x + 1 -‐> r1 Store r1 at y Load from z into r2 In a linearizable system – with an external observer, you would need to do these operations one at a time, wait until each is complete before starting the next. On a modern single processor CPU, though, these four instructions can execute in parallel – except for the use of x in step 2, and the use of r1 in step 3, everything is independent, provided you can guarantee that z != x or y, you can start the load before the other instructions have finished. So a modern CPU will buffer the write at step 1, do step 2, do step 3 when step 2 is done, and do the load in parallel with steps 1-‐3, after checking the addresses are different. But if there is...
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This document was uploaded on 04/04/2014.
- Spring '14