c31 lecture 16

G convey hc 1 eg tegra 2 high performance good energy

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: c. SOC, etc. (e.g., Convey HC-1) (e.g., Tegra 2) High performance; good energy efficiency Low power, good energy efficiency Diamondvill e C0 C1 C0 C1 L1 L1 cache cache L1 L1 cache cache L2 cache L2 cache Harpertown C2 C2 C3 C3 C4 C4 C5 C5 L1 L1 cache cache L1 L1 cache cache L1 L1 cache cache Mobile components in server platforms L1 L1 cache cache L2 cache L2 cache L2 cache L2 cache FSB FSB Memory control Memory control Memory Memory QuickIA Platform courtesy of Intel RF Interconnects High bandwidth, programmable interface 46 Software stack: compilers (source: SciDAC) 47 CDSC compiler(s) Write-once-run-everywhere Describe the organization of the application steps with a graph Write each step using an easy-to-write language Describe the machine Call the compiler! Looking easy? Already needs 5.7 millions lines of codes and counting! 48 Proposed Mapper Infrastructure 49 Proposed Mapper Infrastructure Domain Expert Hardware Expert provides CnC-based description of the application provides accurate fine-grain description of the platform Application CHP Hardware description HPT CnC Translator Matlab->HC Tuning Experts guide/refine the mapping decisions based on performance … HC translator High-Level transfo. Polyhedral … Stencil DSL compiler LLVM Opt. OpenCL compiler Unified Runtime High-level Synthesis ... CHP simulator Convey Testbed ... Input to the mapper Higher-level translators layer High-level compilation layer Low-level / target-specific compilation layer Execution layer 50 Higher-Level Compilation Layer Input application Tuning Expert provides CnC annotations Steps written in: CnC graph (data/task flow) Matlab CnC translator Matlab to HC HC HC eSDSL OpenCL C CHP Hardware description HPT creation (by expert) eSDSL OpenCL C HPT (XML) 51 High-level Compilation Layer HC OpenCL C eSDSL ROSE Parser (to Sage IR) Tuning Expert HPT input to all modules High-Level transformations engine (tiling, scalar opt., etc.) Polyhedral compiler Can guide mapping decisions High-level Synthesis compiler Stencil DSL compiler Feedback from lower layers: LLVM cost metrics, performance feedback, QoR from AutoESL, … HabaneroC translator ROSE Unparser / Rose SAGE IR Sage IR C OpenCL 52 Low-Level Compilation Layer Sage IR Tuning Expert RoseToLLVM LLVM IR Feedback to upper layer (cost metrics) C (AutoESL) LLVM IR RTL for prog. fabric Can fine-tune optim. decisions SIMD vect. Other LLVM opts. Executable CPU/core code LLVM H/W desc. input to LLVM and AutoESL RTL synthetiser Clang Accel. Lib. Extract. OpenCL Fixed accelerator libraries (Xilinx ISE) OpenCL compiler (vendor) FPGA bitstream Feedback from lower layer: performance GPU code RTL to FPGA with calls to Accel. lib 53 Execution Layer Executable CPU/core code Feedback to upper layer (performance) FPGA bitstream GPU code Unified Adaptive Runtime system (schedules tasks across CPUs, GPUs, Accelerators, FPGA processors) Performance feedback Convey HC-1 testbed CHP simulator 54 So, what for you? If your application targets a handheld device Likely, will be about interacting with the user, and displaying data Will need to connect to the cloud for intense computing May be Java, or even computer-assisted design Or, you may be a hardcore/performance programmer… If your application targets the cloud No idea about the actual hardware running Still use a generic language (Java, C++?) 55...
View Full Document

This note was uploaded on 04/03/2014 for the course CS 31 taught by Professor Melkanoff during the Fall '00 term at UCLA.

Ask a homework question - tutors are online