EXAM 5-solution - EE348EXAM5NAME:SOLUTION 9.08.2011SURNAME...

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EE348 EXAM 5 NAME: SOLUTION 9.08.2011 SURNAME: Q1) (14 pts) UP DOWN CLK Operation 0 0 x No Change 1 x Count UP 0 1 Count DOWN You are requested to design a 4 bit binary UP‐ DOWN ripple counter, which will count by the arrival of negative edge of clk pulse as given in the table. Make necessary connections below, by using minimum number of additional gates. 0 and 1 signals are available. Notice that FF types are different and also some of the them are negative edge triggered while others are positive edge triggered. which can be simlified as Q2) (7 pts) You are given binary counter with parallel load . Make necessary connections so that it will count the sequence 2,3,4,5,6. Use minimum number of additional gates. 0 and 1 signals are available carry out = A 3 A 2 A 1 A 0 Clear CP Load Count Function 0 x x x Clear to 0 1 x 0 0 No change 1 1 x Load Input 1 0 1 Count next binary state Q D C Q’ Q S C Q’ R UP DOWN CLK A 2 A 1 A 0 Q T C Q’ 0 0 1 0 CP clear A 3 A 2 A 1 A 0 BINARY COUNTER I 3 I 2 I 1 I 0 load count carry out 1 1 Clk Q D C Q’ Q S C Q’ R UP DOWN CLK A 2 A 1 A 0 Q T C Q’
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EE348 EXAM 5 NAME: SOLUTION 9.08.2011 SURNAME: Q3) (14 pts) There are two 3 bit registers A and B with
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