EXAM 4-solution - EE348Summer2011NAME:SOLUTION EXAM4SURNAME...

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Q1)a) (5 pts) Draw state transition diagram for the sequential circuit which will produce serially the 2's complements of n bit numbers fed to the circuit serially (LSB being first) from input Xd. Another input Xf signals the arrival of the nth bit. ... 19 18 17 16 15 14 13 12 11 10 11 6 5 4 3 2 1 0 Time .. 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 Xf ... 0 0 1 1 0 1 1 1 1 0 1 0 0 0 0 1 1 0 Xd 1 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 0 Y b)(10 pts) Draw state transition diagram for the sequential circuit that produces output 1 iff the last three bits arrived are all 0 or all 1, i.e. X n‐2 X n‐1 X n =000 or X n‐2 X n‐1 X n =111 Example Time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ... X 0 0 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 0 ... Y 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 00 11 10 01 0/1 0/0 1/0 0/0 0/0 1/1 1/0 1/0 a b 00/0, 10/0, 11/1 00/1, 01/0 10/1, 11/0 01/1 XfXd/Y 2's COMPLEMENTER Xf Xd y ALL SAME X y EE 348 Summer 2011 NAME: SOLUTION EXAM 4 SURNAME
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Q2) (10 pts) NS Output PS x=0 x=1 x=0 x=1 a c h 0 1 b d d 0 1 c c a 1 0 d f a 0 1 e e f 1 0 f f e 1 0 g g h 1 0 h c a 0 1 Given the state transition table, apply state reduction by partitioning algorithm to find out the equivalent states S 1 1 = {
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EXAM 4-solution - EE348Summer2011NAME:SOLUTION EXAM4SURNAME...

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