main memory 0 1 2 3 4 5 6 7 8 m 1 data

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Unformatted text preview: ity of Washington Indexing into the “DRAM Cache” CPU Chip CPU Virtual address (VA) MMU Physical address (PA) ... Main memory 0: 1: 2: 3: 4: 5: 6: 7: 8: M-­‐1: Data word How do we perform the VA -­‐> PA translaKon? Virtual Memory as Cache University of Washington Address TranslaMon: Page Tables ¢  A page table (PT) is an array of page table entries (PTEs) that maps virtual pages to physical pages. Physical memory (DRAM) Physical page number or Valid disk address PTE 0 0 null 1 1 0 1 0 0 PTE 7 1 VP 1 VP 2 VP 7 VP 4 Virtual memory (disk) null VP 1 Memory resident page table (DRAM) VP 2 VP 3 How many page tables are in the system? One per process Virtual Memory as Cache VP 4 VP 6 VP 7 PP 0 PP 3 University of Washington Address TranslaMon With a Page Table Page table base register (PTBR) Page table address for process Virtual address (VA) Virtual page number (VPN) Virtual page offset (VPO) Page table Valid Physical page number (PPN) Valid bit = 0: page not in memory (page fault) In most cases, the hardware (the MMU) can perform this translaMon on its own, without sosware assistance Physical page number (PPN) Physical address (PA) Virtual Memory as Cache Physical page offset (PPO) University of Washington Page Hit ¢  Page hit: reference to VM byte that is in physical memory Virtual address Physical page number or Valid disk address PTE 0 0 null 1 1 0 1 0 0 PTE 7 1 null Physical memory (DRAM) VP 1 VP 2 VP 7 VP 4 Virtual memory (disk) VP 1 Memory resident page t...
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This document was uploaded on 04/04/2014.

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