Hierarchy core 2 duo not drawn to scale l1l2 cache 64

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Unformatted text preview: ached in DRAM Virtual Memory as Cache University of Washington Memory Hierarchy: Core 2 Duo Not drawn to scale L1/L2 cache: 64 B blocks ~4 MB L2 unified cache L1 I-­‐cache 32 KB CPU Reg L1 D-­‐cache Throughput: 16 B/cycle Latency: 3 cycles 8 B/cycle 14 cycles ~4 GB Main Memory 2 B/cycle 100 cycles ~500 GB 1 B/30 cycles millions Miss penalty (latency): 33x Miss penalty (latency): 10,000x Virtual Memory as Cache Disk University of Washington DRAM Cache OrganizaMon ¢  DRAM cache organizaMon driven by the enormous miss penalty §  DRAM is about 10x slower than SRAM §  Disk is about 10,000x slower than DRAM §  ¢  (for first byte; faster for next byte) Consequences? §  Block size? §  AssociaKvity? §  Write-­‐through or write-­‐back? Virtual Memory as Cache University of Washington DRAM Cache OrganizaMon ¢  DRAM cache organizaMon driven by the enormous miss penalty §  DRAM is about 10x slower than SRAM §  Disk is about 10,000x slower than DRAM §  ¢  (for first byte; faster for next byte) Consequences §  Large page (block) size: typically 4-­‐8 KB, someKmes 4 MB §  Fully associaKve Any VP can be placed in any PP §  Requires a “large” mapping funcKon – different from CPU caches §  Highly sophisKcated, expensive replacement algorithms §  Too complicated and open-­‐ended to be implemented in hardware §  Write-­‐back rather than write-­‐through §  Virtual Memory as Cache Univers...
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This document was uploaded on 04/04/2014.

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