G read only library code university of washington

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Unformatted text preview: i: Valid VP 0: VP 1: VP 2: Process j: VP 0: VP 1: VP 2: Yes Yes Yes SUP WRITE EXEC Yes No Yes No No Yes No Yes No • • • Valid SUP WRITE EXEC Yes No Yes No Yes Yes Yes No Yes No No No Address PP 6 PP 4 PP 2 Physical Address Space PP 2 PP 4 PP 6 Address PP 9 PP 6 PP 11 Address TranslaMon PP 8 PP 9 PP 11 University of Washington Address TranslaMon: Page Hit 2 PTEA CPU Chip CPU 1 VA PTE MMU 3 PA Cache/ Memory 4 Data 5 1) Processor sends virtual address to MMU (memory management unit) 2-­‐3) MMU fetches PTE from page table in cache/memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor Address TranslaMon University of Washington Address TranslaMon: Page Fault ExcepMon 4 2 PTEA CPU Chip CPU 1 VA 7 Page fault handler MMU PTE 3 VicMm page Cache/ Memory 5 Disk New page 6 1) Processor sends virtual address to MMU 2-­‐3) MMU fetches PTE from page table in cache/memory 4) Valid bit is zero, so MMU triggers page fault excepKon 5) Handler idenKfies vicKm (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarKng faulKng instrucKon Address TranslaMon University of Washington Hmm… TranslaMon Sounds Slow! ¢  The MMU accesses memory twice: once to first get the PTE for translaMon, and then again for the actual memory request from the CPU §  The PTEs may be cached in L1 like any other memory word §  §  ¢  But they may be evicted by othe...
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This document was uploaded on 04/04/2014.

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