University of washington intel i7 die 02 may 2012

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Unformatted text preview: p L1 cache (SRAM) L1 cache holds cache lines retrieved from L2 cache off ­chip L2 cache (SRAM) main memory (DRAM) local secondary storage (local disks) remote secondary storage (distributed file systems, web servers) Caches  ­ Memory Hierarchy L2 cache holds cache lines retrieved from main memory Main memory holds disk blocks retrieved from local disks Local disks hold files retrieved from disks on remote network servers University of Washington Intel Core i7 Cache Hierarchy Processor package Core 0 Core 3 Regs L1 d-cache Regs L1 i-cache L1 d-cache … L2 unified cache L1 i-cache L2 unified cache L3 unified cache (shared by all cores) Main memory Caches  ­ Memory Hierarchy L1 i ­cache and d ­cache: 32 KB, 8 ­way, Access: 4 cycles L2 unified cache: 256 KB, 8 ­way, Access: 11 cycles L3 unified cache: 8 MB, 16 ­way, Access: 30 ­40 cycles Block size: 64 bytes for all caches. University of Washington Intel i7 Die 02 May 2012 Memory Organiza?on 25 University of Washington Memory and Caches           Cache basics Principle of locality Memory hierarchies Cache organiza?on Program op?miza?ons that consider caches Cache Organiza?on University of Washington Where should we put data in the cache? Memory 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111   Cache Index 00 01 10 11 How can we compute this mapping? Cache Organiza?on Data University of Washington Where should we put data in the cache? Memory 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Cache Index 00 01 10 11 Data Hmm.. The cache might get confused later! Why? And how do we solve that? Cache Organiza?on University of Washington Use tags! Memory 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Cache Index 00 01 10 11...
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This document was uploaded on 04/04/2014.

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