Es of hardware and sonware systems faster storage

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Unformatted text preview: Performance Metrics   Miss Rate   Frac:on of memory references not found in cache (misses / accesses) = 1  ­ hit rate   Typical numbers (in percentages):   3%  ­ 10% for L1   Hit Time   Time to deliver a line in the cache to the processor Includes :me to determine whether the line is in the cache   Typical hit :mes: 1  ­ 2 clock cycles for L1     Miss Penalty   Addi:onal :me required because of a miss   Typically 50  ­ 200 cycles Caches  ­ Memory Hierarchy University of Washington Memory Hierarchies   Some fundamental and enduring proper?es of hardware and sonware systems:   Faster storage technologies almost always cost more per byte and have lower capacity   The gaps between memory technology speeds are widening   True for: registers ↔ cache, cache ↔ DRAM, DRAM ↔ disk, etc.   Well ­wriTen programs tend to exhibit good locality     These proper?es complement each other beau?fully They suggest an approach for organizing memory and storage systems known as a memory hierarchy Caches  ­ Memory Hierarchy University of Washington Memory Hierarchies   Fundamental idea of a memory hierarchy:   Each level k serves as a cache for the larger, slower, level k+1 below.   Why do memory hierarchies work?   Because of locality, programs tend to access the data at level k more oeen than they access the data at level k+1.   Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit.   Big Idea: The memory hierarchy creates a large pool of storage that costs as much as the cheap storage near the bo\om, but that serves data to programs at the rate of the fast storage near the top. Caches  ­ Memory Hierarchy University of Washington An Example Memory Hierarchy registers Smaller, faster, costlier per byte Larger, slower, cheaper per byte CPU registers hold words retrieved from L1 cache on ­chi...
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