On university of washington intel core i7 cache

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Unformatted text preview: mpulsory) miss   Occurs on first access to a block   Conflict miss   Most hardware caches limit blocks to a small subset (some:mes just one) of the available cache slots   if one (e.g., block i must be placed in slot (i mod size)), direct ­mapped   if more than one, n ­way set ­associa:ve (where n is a power of 2)   Conflict misses occur when the cache is large enough, but mul:ple data objects all map to the same slot   e.g., referencing blocks 0, 8, 0, 8, ... would miss every :me   Capacity miss   Occurs when the set of ac:ve cache blocks (the working set) is larger than the cache (just won’t fit) Cache Organiza?on University of Washington What about writes?   Mul?ple copies of data exist:   L1, L2, possibly L3, main memory   What is the main problem with that? Cache Organiza?on University of Washington What about writes?   Mul?ple copies of data exist:   L1, L2, possibly L3, main memory   What to do on a write ­hit?   Write ­through (write immediately to memory)   Write ­back (defer write to memory un:l line is evicted)     Need a dirty bit to indicate if line is different from memory or not What to do on a write ­miss?   Write ­allocate (load into cache, update line in cache) Good if more writes to the loca:on follow   No ­write ­allocate (just write immediately to memory)     Typical caches:   Write ­back + Write ­allocate, usually   Write ­through + No ­write ­allocate, occasionally Cache Organiza?on University of Washington Intel Core i7 Cache Hierarchy Processor package Core 0 Core 3 Regs L1 d-cache Regs L1 i-cache L1 d-cache … L2 unified cache L1 i-cache L2 unified cache L3 unified cache (shared by all cores) Main memory Cache Organiza?on L1...
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This document was uploaded on 04/04/2014.

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