Unformatted text preview: arallel ComputaCon Winter 2013: Chamberlain 34 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Adve) Ini!ally, x == 0, y == 0 Task 1 Task 2 reg1 = x reg2 = y y = 1 x = 2 What about reg1 = 2, reg2 = 1 ? The “blame the hardware” explana3on: • Processors typically don’t serialize memory ops (parCcularly on large‐scale machines) • In pracCce, independent memory ops can have diﬀerent latencies / be reordered in HW • analogous to compiler situaCon: HW doesn’t know about all other tasks y Task 1 reg1 = x y = 1 memory c c c socket node CSEP 524: Parallel ComputaCon x memory c network Winter 2013: Chamberlain c c c socket node c Task 2 reg2 = y x = 2 35 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Adve) Ini!ally, x == 0, y == 0 Task 1 Task 2 reg1 = x reg2 = y y = 1 x = 2 What about reg1 = 2, reg2 = 1 ? The “blame the hardware” explana3on: • Processors typically don’t serialize memory ops (parCcularly on large‐scale machines) • In pracCce, independent memory ops can have diﬀerent latencies / be reordered in HW • analogous to compiler situaCon: HW doesn’t know about all other tasks y Task 1 reg1 = x y = 1 memory c c c socket node CSEP 524: Parallel ComputaCon memory ﬁre oﬀ load of x c c ﬁre oﬀ load of y Winter 2013: Chamberlain x c c socket node c Task 2 reg2 = y x = 2 36 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Adve) Ini!ally, x == 0, y == 0 Task 1 Task 2 reg1 = x reg2 = y y = 1 x = 2 What about reg1 = 2, reg2 = 1 ? The “blame the hardware” explana3on: • Processors typically don’t serialize memory ops (parCcularly on large‐scale machines) • In pracCce, independent memory ops can have diﬀerent latencies / be reordered in HW • analogous to compiler situaCon: HW doesn’t know about all other tasks y Task 1 reg1 = x y = 1 memory c c c socket node CSEP 524: Parallel ComputaCon memory load of x conCnues c c load of y conCnues Winter 2013: Chamberlain x c c socket node c Task 2 reg2 = y x = 2 37 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Adve) Ini!ally, x == 0, y == 0 Task 1 Task 2 reg1 = x reg2 = y y = 1 x = 2 What about reg1 = 2, reg2 = 1 ? The “blame the hardware” explana3on: • Processors typically don’t serialize memory ops (parCcularly on large‐scale machines) • In pracCce, independent memory ops can have diﬀerent latencies / be reordered in HW • analogous to compiler situaCon: HW doesn’t know about all other tasks y Task 1 reg1 = x y = 1 memory c c c socket node CSEP 524: Parallel ComputaCon memory load of x arrives c c load of y arrives Winter 2013: Chamberlain x c c socket node c Task 2 reg2 = y x = 2 38 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Adve) Ini!ally, x == 0, y == 0 Task 1 Task 2 reg1 = x reg2 = y y = 1 x = 2 What about reg1 = 2, reg2 = 1 ? The “blame the hardware” explana3on: • Processors typically don’t serialize memory ops (parCcularly on large‐scale machines) • In pracCce, independent memory ops can have diﬀerent latencies / be reordered in HW • analogous to compiler situaCon: HW doesn’t know about all other tasks y Task 1 reg1 = x y = 1 memory c c c socket node CSEP 524: Parallel ComputaCon memory load of x got 2 c c load of y got 1 Winter 2013: Chamberlain x c c socket node c Task 2 reg2 = y x = 2 39 Mo3va3ng Example (adapted from The Java MCM: Manson, Pugh, Ad...
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