It can yield a signicant fracion of peak performance

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Unformatted text preview: lel RAM) ignores memory organization, collisions, latency, conflicts, etc. o༆  Ignoring these are claimed to have benefits ... n༆  Portable everywhere since it is very general n༆  It is a simple programming model ignoring only insignificant details -- off by “only log P” n༆  Ignoring memory difficulties is OK because hardware can “fake” a shared memory n༆  Good for getting started: Begin with PRAM then refine the program to a practical solution if needed 58 Source: Larry Snyder, CSEP524, UW Variations on PRAM Resolving the memory conflicts considers read and write conflicts separately o༆  Exclusive read/exclusive write (EREW) o༆  The most limited model o༆  Concurrent read/exclusive write (CREW) o༆  Multiple readers are OK o༆  Concurrent read/concurrent write (CRCW) o༆  Various write-conflict resolutions used o༆  There are at least a dozen other variations All theoretical -- not used in practice Source: Larry Snyder, CSEP524, UW 59 CTA Model o༆  Candidate Type Architecture: A model with P standard processors, d degree, λ latency RAM RAM RAM RAM RAM … RAM Interconnection Network o༆  Node == processor + memory + NIC Key Property: Local memory ref is 1, global memory is λ Source: Larry Snyder, CSEP524, UW What CTA Doesn’t Describe o༆  CTA has no global memory … but memory could be globally addressed o༆  Mechanism for referencing memory not specified: shared, message passing, 1-side o༆  Intercon...
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