In 2002 have worked primarily on chapel an emerging

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Unformatted text preview: following Moore’s Law •  But clock speeds have stopped increasing as rapidly as historically •  So what to do with extra transistors? And how to provide the performance boosts we’re used to? •  Answer: add parallelism CSEP 524: Parallel ComputaEon Winter 2013: Chamberlain 22 Source: The Free Lunch is Over, Herb Suber, hbp:// ddj.htm Prototypical Next- Gen Processor Technologies Intel MIC AMD Trinity Nvidia Echelon Tilera Tile- Gx CSEP 524: Parallel ComputaEon Winter 2013: Chamberlain Sources: hbp://, hbp:// trinity- processors- take- on- intels- ivy- bridge- 3040155225/, hbp:// reveals- details- of- echelon- gpu- designs- for- exascale/, hbp:// Gx%203036%20SB012- 01.pdf 23 General Characteris3cs of These Architectures •  Increased hierarchy and/or sensiEvity to locality •  PotenEally heterogeneous processor/memory types •  Increasingly resemble supercomputers- on- a- chip ⇒ Next- gen programmers will have a lot more to think about at the node level than in the past CSEP 524: Parallel ComputaEon Winter 2013: Chamberlain 24 Outline for Today ü༏  Parallel CompuEng: DefiniEon and MoEvaEon •  Introductory stuff –  A lible about me –  Course overview •  Metrics for parallel execuEon •  Algorithm: Embarrassingly Parallel ComputaEon •  Programming Models: –  POSIX threads –  Chapel •  This week’s assignment CSEP 524: Parallel ComputaEon Winter 2013: Chamberlain 25 Me My Parallel Compu3ng Background Graduated from UW in 2001 –  dissertaEon focused on ZPL •  an array- based parallel language developed at UW during the 1990’s –  advisor: Larry Snyder •  he taught this course unEl he reEred •  he also co- authored our textbook Spent an educa3onal year at a start- up –  worked on a parallel language for embedded compuEng Joined Cray Inc....
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