22 cache memory is an extremely fast small memory

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Unformatted text preview: . RAM chips are of two types - dynamic and static. A dynamic RAM {DRAM), uses an external circuitry to periodically "regenerate" or refresh the storage charge to retain the stored data. 19. A special type of RAM, called read-only memory (ROM) is a non-volatile memory chip in which data are stored permanently and cannot be altered by the programmer. There are two types of read-only memory (ROM) - manufacturer-programmed and userprogrammed. The latter is commonly known as Programmable Read-Only Memory (PROM) because a user can program it. 20. Once information is stored in a ROM chip or a PROM chip it cannot be altered. However, Erasable Programmable Read-Only Memory (EPROM) chips can be reprogrammed to store new information. EPROM chips are of two types - Ultra Voilet EPROM(UVEPROM) and Electrically EPROM(EEPROM). EEPROM is also known as flash memory. 21. The overall performance of a processor can be greatly improved by minimizing the memory-processor speed mismatch. The two commonly used approaches for minimizing the memory-processor speed mismatch are the use of cache memory and memory interleaving. 22. Cache memory is an extremely fast, small memory between CPU and main memory whose access time is closer to the processing speed of the CPU. It acts as a high-speed buffer between CPU and main memory and is used to temporarily store very active data and instructions during processing. 23. The connectivity channel used for interaction between the CPU and memory is known as a bus. Physically, a bus is a set of wires, which carries a group of bits in parallel and has an associated control scheme. The bus width is defined as the number of parallel lines (wires) in the bus. Every computer system has the following three types of buses - data bus, address bus and control bus. l 24. Just like the buses between the CPU and memory, every computer system also uses buses for interconnecting the CPU (with I/O devices. The same three types of buses (data bus, address bus and control bu...
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This document was uploaded on 04/07/2014.

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