# 29c with the number inside each nand gate identifying

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Unformatted text preview: OR gate is substituted by two input inverters followed by a NAND gate. Thus each AND gate is substituted by two NAND gates and each OR gate is substituted by three NAND gates. The logic diagram so obtained is shown in Figure 6.29(b). Note that Figure 6.29(b) has seven inverters (single input NAND gates) and five two-input NAND gates. Each two-input NAND gate has a number inside the gate symbol for identification purpose. Pairs of inverters connected in cascade (from each AND box to each OR box) are removed since they form double inversion, which has no meaning. The inverter connected to input A is removed and the input variable is changed from A to A . The result is the NAND logic diagram shown in Figure 6.29(c), with the number inside each NAND gate identifying the gate from Figure 6.29(b). This example demonstrates that the number of NAND gates required to implement the Boolean function is equal to the number of AND/OR gates, provided both the normal and complement inputs are available. Otherwise inverters must be used to generate any required complemented inputs. Example 6.14. Construct a logic circuit for the Boolean expression (A + E) • (B + C • D) using only NAND gates. Solution: The AND/OR implementation for the given Boolean expression is drawn in Figure 6.30(a). Now the NAND equivalent of each AND and each OR gate is substituted resulting in Figure 6.30(b). Note that Figure 6.30(b) has six inverters (single input NAND gates) and four two-input NAND gates. One pair of cascaded inverters may be removed. Also the three external inputs A, B, and E, which go directly to inverters, are complemented and the corresponding inverters are removed. The final NAND gate implementation so obtained is shown in Figure 6.30(c). The number inside each NAND gate of Figure 6.30(c) corresponds to the NAND gate of Figure 6.30(b) having the same number. For this example, the number of NAND gates required is equal to the number of AND/OR gates plus an additional inverter at the output (NAND gate number 5). In general, the number of NAND gates required to implement a Boolean function equals th...
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## This document was uploaded on 04/07/2014.

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