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Unformatted text preview: e is used to carry the device address. Hence in the figure, they
have been specifically named as Memory Address Bus (MAB) and Device Address Bus
(DAB). The DMA controller has a data register to temporarily store the data being transferred, a memory address register to keep track of the memory location from/to
where data is transferred, a counter to keep track of how many memory words have to be
transferred, a "busy" indicator to indicate that it is currently busy and cannot accept any
new I/O requests now, and a "data ready" indicator to indicate to the CPU that the
requested data is ready in its data register for transfer.
The data transfer in this case takes place in the following manner:
1. The CPU sends the I/O request (say a data READ request) to the DMA controller.
The device address of the device from which data is to be read, the memory location at
which data is to be stored, and the READ command along with the number of memory
words to be read are sent across by using the device address bus, the memory address
bus, and the control bus respectively. After sending the request, the CPU continues with
its normal course of execution since it has no further direct role in this I/O request
2. On receiving the request, the DMA controller sets its "busy" indicator to ON and
stores the received
memory address and number of memory words to be read in its memory address register
and the counter respectively.
3. It then reads the first memory word to be transferred from the specified I/O device
into its data register and sets the "data ready" indicator to ON.
4. It now sends an interrupt signal to the CPU.
5. On receiving the interrupt signal, the CPU completes the execution of the instruction
that it is currently executing, and then yields the memory address and data buses to the
DMA controller for one memory cycle.
6. The DMA controller transfers the data in its data register to the memory location
specified" by the contents...
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- Spring '14