Unformatted text preview: cture. The three commonly used interconnection architectures are described below.
As shown in Figure 7.10, in the unibus architecture there is a single data bus, a single
address bus, and a single control bus used to interconnect the CPU with both the memory
and I/O devices. That is, the buses are shared for data transfer between the CPU and
memory, as well as between the CPU and I/O devices. As a result, data transfer can take
place at a time only between CPU and memory, or between CPU and an I/O device.
Obviously, this architecture leads to a very slow data transfer. Hence it is used mostly in
small computers where performance is not an issue. The main advantage of this
architecture is its simple design and ease of programming of I/O device accesses. In this
case, I/O devices do not require any special I/O instructions because they use the same
memory address space. Hence a WRITE instruction with an address corresponding to an
output device will write information to that device. Another advantage of this architecture
is that it allows new I/O devices to be easily added to the system, as no new instructions
specific to the device are required.
Dual Bus Architecture
As shown in Figure 7.11, in the dual bus architecture, there are separate set of buses for
interconnecting the CPU with memory and with I/O devices. Hence data transfer between
the CPU and main memory is carried out by using the buses which interconnect the CPU
and main memory, while data transfer between the CPU and I/O devices is carried out by
using the buses which interconnect the CPU and I/O devices. In this case, one of the
following two mechanisms are used for data transfer between the CPU and an I/O device:
1. Busy Wait. In this method, the CPU sends the I/O request (say a data READ request)
to the device via the buses. As already described, the command and the device address
associated with the READ request are sent across by using the control bus and the
address bus respectively. As soon as the device controller receives the request, it first sets
View Full Document
This document was uploaded on 04/07/2014.
- Spring '14