Unformatted text preview: hat can address
232 bytes (over 4 billion bytes), or 4 GB, of memory.
3. Control Bus. In addition to sending addresses and exchanging data with the memory,
the CPU also needs to send control signals to the memory to specify whether the data is
to be read from or written to the specified address location. Such signals, which are in
the form of READ/WRITE commands, are carried by the control bus.
Thus a memory access by the CPU involves all the three buses - the memory access
command is carried by the control bus, the memory address is carried by the address bus,
and the data to be transferred is carried by the data bus. Figure 7.8 shows the three buses
used for interconnecting the CPU and main memory for enabling this.
Address Bus Control Bus
Figure 7.8. The three types of buses used between the CPU and main memory.
We saw in Chapter 2 that in addition to the flow of data between the CPU and memory,
data also flows between the CPU and I/O devices in a computer system. Hence just like
the buses between the CPU and memory, every computer system also uses buses for
interconnecting the CPU with I/O devices. The same three types of buses used for
interconnecting the CPU and memory are also used for interconnecting the CPU with I/O
devices. Their roles in context of I/O devices are described below.
1. Data Bus. The data bus is used to transfer data between the CPU and I/O devices. As
discussed before, a wider data bus will enable faster exchange of data between the CPU
and I/O devices. The commonly used, industry standard data buses are as follows:
- ISA Bus. ISA stands for Industry Standard Architecture. It is a 16-bit bus but that
can transmit data along either 8 or 16 data lines, depending on what kind of adapter card
is used in an expansion slot. That is, ISA expansion slots can accept both 8-bit and 16-bit
MCA Bus. MCA stands for Micro Channel Architecture. It is a 32-bit bus that
transmits data along 32 data lines. Du...
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This document was uploaded on 04/07/2014.
- Spring '14