Hence the cpu is fully involved in every data

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Unformatted text preview: and resumes execution of the job that had made the I/O request. Notice that the interrupt mechanism is more difficult to implement than the busy wait mechanism because it requires a mechanism to suspend a currently executing job and resume it at a later time. How this is done will be discussed in Chapter 14. Moreover, in case of multiple I/O devices, it also requires a mechanism to distinguish among the interrupt signals of different devices and to attend to them based on some priority rules because various devices can initiate interrupt signals independent of each other. DMA Architecture I/O devices are used to input data to or output data from a computer system. Most of the time, this involves either reading data from an input device and storing it in the main memory, or reading data stored in the main memory and outputting it to an output device. That is, data transfer takes, place between the main memory and I/O devices. We saw that in the previous two interconnection architectures, every data transfer to or from an I/O device is carried out by the CPU. Hence the CPU is fully involved in every data transferred between the main memory and I/O devices. This leads to inefficient usage of the CPU. Thus another interconnection architecture, called Direct Memory Access (DMA) architecture, which minimizes the CPU participation in I/O data transfer is often used. As shown in Figure 7.12, in this method an additional hardware called DMA controller [also known as Peripheral Processing Unit (PPU)] is used. All the I/O devices are connected to the DMA controller. A set of buses is used to connect the CPU and memory. Another set of buses is used to directly connect the DMA controller with both the CPU and memory so that data transfer to or from I/O devices can be directly carried out either with the CPU or with the memory. An additional address bus is used between the CPU and the DMA controller. Out of the two address buses, one is used to carry the memory address and the other on...
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This document was uploaded on 04/07/2014.

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