However the method is quite effective in minimizing

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Unformatted text preview: emory addresses and places them in the n MARs in the right order. A memory read command reads all the n memory modules simultaneously, retrieves the n consecutive instructions, and loads them into the n instruction registers. Thus each fetch for a new instruction results in the loading of n consecutive instructions in the n instruction registers of the CPU. Since the instructions are normally executed in the sequence in which they are written, the availability of n successive instructions in the CPU avoids memory access after each instruction execution, and the total execution time speeds up. Obviously, the fetched successive instructions are not useful when a branch instruction is encountered during the course of execution. This is because the new set of n successive instructions starting from the location of the instruction to which the control branches will be loaded into the n instruction registers, overwriting the previously stored instructions which were loaded but some of which were not executed. However, the method is quite effective in minimizing the memory-processor speed mismatch because branch instructions do not occur frequently in a program. Hybrid Approach This method uses both cache memory and memory interleaving. Cache memory is used to reduce the speed mismatch between the CPU and the main memory, and memory interleaving is used to reduce the speed mismatch between the CPU and the cache memory. This approach further helps in speeding up the total execution time. MEMORYBUSES We saw in the discussion above that the data and instructions of a program being executed are stored in the memory and are fetched and loaded into the CPU registers as the program execution proceeds. That is, the interaction between the CPU and memory takes place very frequently. To enable this interaction, some type of connectivity is needed between the two units of a computer system. This connectivity channel is known as a bus. Physically, a bus is a set of wires, which carries a group of bits in para...
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This document was uploaded on 04/07/2014.

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