This preview shows page 1. Sign up to view the full content.
Unformatted text preview: niversal gate because it is
alone sufficient to implement any Boolean function.
To show that any Boolean function can be implemented with the sole use of NAND
gates, we need to only show that the logical operations AND, OR, and NOT can be
implemented with NAND gates. This is shown in Figure 6.28 below.
A NOT operation is obtained from a oneinput NAND gate. Hence, a singleinput NAND
gate behaves as an inverter.
The AND operation requires two NAND gates. The first one produces the inverted AND
and the second one being a single input NAND gate, acts as an inverter to obtain the
normal AND output.
For the OR operation, the normal inputs A and B are first complemented using two single
input NAND gates. Now the complemented variables are fed as input to another NAND
gate, which produces the normal ORed output.
The implementation of Boolean functions with NAND gates may be obtained by means
of a simple block diagram manipulation technique. The method requires that two other
logic diagrams be drawn prior to obtaining the NAND logic diagram. The following steps
are to be carried out in sequence:
Step 1:
From the given algebraic expression, draw the logic diagram with AND, OR,
and NOT gates. Assume that both the normal (A) and complement (A) inputs are
available.
Step 2: Draw a second logic diagram with the equivalent NAND logic substituted for
each AND, OR, and NOT gate.
Step 3: Remove any two cascaded inverters from the diagram since double inversion does
not perform any logical function. Also remove inverters connected to single external
inputs and complement the corresponding input variable. The new logic diagram so
obtained is the required NAND gate implementation of the Boolean function.
Example 6.13.
Construct a logic circuit for the Boolean expression A • B + C • (A + B • D) using only
NAND gates. Solution:
The AND/OR implementation for the given Boolean expression is drawn in Figure
6.29(a). Now each AND gate is substituted by a NAND gate followed by an inverter and
each...
View
Full
Document
This document was uploaded on 04/07/2014.
 Spring '14

Click to edit the document details