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Unformatted text preview: e to its wider bus width, it is significantly faster
than the ISA bus. However, MCA expansion slots cannot accept 8-bit or 16-bit adapter
cards and require specifically designed 32-bit adapter cards.
EISA Bus. EISA stands for Extended Industry Standard Architecture. Since the
expansion slots that fit into an ISA bus could not work with the MCA bus, the MCA bus
had the problem of upward compatibility. EISA bus was designed to solve this problem.
Hence like MCA, EISA is also a 32-bit bus. However, unlike MCA, it was designed to
accept and use the old ISA expansion slots. The EISA is faster than the ISA, but not as
fast as the MCA -the price of its compatibility with the older 16-bit expansion slots.
2. Address Bus. A computer system normally has multiple I/O devices like disk, tape,
network, etc. simultaneously connected to it. Each I/O device has a unique identifier (or
address) associated with it. The address bus is used to carry the address of the I/O device
to be accessed by the CPU.
3. Control Bus. The control bus is used to carry commands such as START, READ,
WRITE, REWIND TAPE, etc., from the CPU to I/O devices. It is also used to carry the
status information of the I/O devices to the CPU.
Thus an I/O device access by the CPU involves all the three buses - the device access
command is carried by the control bus, the device address is carried by the address bus,
and the data to be transferred is carried by the data bus. Figure 7.9 shows the three buses
used for interconnecting the CPU and I/O devices for enabling this. Each device has a
controller, which controls the operation of the device. It also temporarily stores the data
transferred between the CPU and the device in a local data register.
INTERCONNECTION ARCHITECTURES In the discussion above, we saw the use of buses in interconnecting the CPU with
memory and I/O devices. The interconnection architecture defines how exactly these
functional units of a computer system are connected to each other. The accessing
mechanism and the flow of data from one unit to another depends on the interconnection
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This document was uploaded on 04/07/2014.
- Spring '14