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Unformatted text preview: aced to make room for the new block. The replacement policy decides
which block to replace in such situation. Obviously, it will be best to replace a block that
is least likely to be needed again in the near future. Although it is impossible to identify
such a block, a reasonably effective strategy is to replace the block that has been in the
cache longest with no reference to it. This policy is referred to as the least recently used
(LRU) algorithm. Hardware mechanisms are needed to identify the least recently used
block. 4. Write policy. If the contents of a block in the cache are altered, then it is necessary to
write it back to main memory before replacing it. The write policy decides when the
altered words of a block are written back to main memory. At one extreme, an updated
word of a block is written to the main memory as soon as such updates occur in the
block. At the other extreme, all updated words of the block are written to the main
memory only when the block is replaced from the cache. The latter policy minimizes
memory write operations but temporarily leaves main memory in an inconsistent
(obsolete) state. This can interfere with multiple-processor operation when multiple
processors share a common memory and cache. It can also interfere with direct memory
access by input/output modules. Several other write policies that are somewhere in
between these two extremes are also in use. The choice of a suitable write policy for a
particular computer architecture is normally left to the designer.
In this method, the main memory is divided into n equal size modules and the CPU has
separate MAR and MBR registers for each memory module. In addition, the CPU has n
instruction registers and a memory access system. When a program is loaded into the
main memory, its successive instructions are stored in successive memory modules. For
example, if n = 4 and the four memory modules are Mi, M 2, M3 and M4, the 1st instruction
will be stored in Mi, 2nd in M2, 3td in M3,"4th in M4, 5th in Mi, 6th in M2, and so on. Now
during the execution of the program, when the processor issues a memory fetch
command, the memory access system creates n consecutive m...
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This document was uploaded on 04/07/2014.
- Spring '14