The name of the former stems from the fact that two

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Unformatted text preview: rithmetic operation for any computer system. Addition in binary system can be summarized by the following four rules: 0+0=0 0+1=1 1 + 0 =1 1 + 1 = 10 The first three operations produce a sum whose length is one digit, but when both augend and addend bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is called a carry. When the augend and addend numbers contain more significant digits, the carry obtained from the addition of two bits is added to the next higher order pair of significant bits. A combinational circuit that performs the addition of two bits is called a half-adder. One that performs the addition of three bits (two significant bits and previous carry) is called a full-adder. The name of the former stems from the fact that two half-adders can be employed to implement a full-adder. Design of Half-Adder From the definition of a half-adder, we find that this circuit needs two binary inputs and two binary outputs. The input variables designate the augend and addend bits whereas the output variables produce the sum and carry bits. Let A and B be the two inputs and S (for sum) and C (for carry) be the two outputs. The truth table of Figure 6.36 exactly defines the function of the half-adder. Inputs Outputs A 0 0 1 B 0 1 0 C 0 0 0 •s 0 1 1 1 1 1 Figure 6.36. Truth table for a half-adder. 0 The simplified Boolean functions for the two outputs, directly obtained from the truth table, are: The logic circuit diagram to implement this is shown in Figure 6.37. The half-adder is limited in the sense that it can add only two single bits. Although it generates a carry for the next higher pair of significant bits, it cannot accept a carry generated from the previous pair of lower significant bits. A full-adder solves this problem. Design of Full-Adder A full-adder forms the arithmetic sum of three input bits. Hence it consists of three inputs and two outputs. Two of the input variables (A and B) represent the augend and the addend bits and the third input variable (D) represents the carry from the previous lower significant p...
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This document was uploaded on 04/07/2014.

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