Lecture13 Sequential Logic.ppt - Sequential Logic[Adapted from Rabaey\u2019s Digital Integrated Circuits \u00a92002 J Rabaey et al EE415 VLSI Design Project

# Lecture13 Sequential Logic.ppt - Sequential Logic[Adapted...

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EE415 VLSI Design Sequential Logic Sequential Logic [Adapted from Rabaey’s Digital Integrated Circuits , ©2002, J. Rabaey et al.]
EE415 VLSI Design Project Presentations What to include in presentation? Reason for choosing the design Final/Intended application Design constraints What it does/How it works Simulations!, Simulations!!, Simulations!!! Layout Post-layout simulations! Achieved goal? Unexpected glitches? Future work Contrast proposed schedule with actual schedule
EE415 VLSI Design Sequential Logic 2 storage mechanisms • positive feedback • charge-based COMBINATIONAL LOGIC Registers Outputs Next state CLK Q D Current State Inputs
EE415 VLSI Design Meta-Stability Gain should be larger than 1 in the transition region A C d B V i2 5V o1 V i1 5V o2 A C d B V i2 5V o1 V i1 5V o2
EE415 VLSI Design Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) CLK 1 0 D Q 0 CLK 1 D Q In Clk Q Clk Q In Clk Q Clk Q
EE415 VLSI Design Mux-Based Latch CLK CLK CLK CLK Q M Q M NMOS only Non-overlapping clocks D
EE415 VLSI Design Mux-Based Latch CLK CLK CLK D Q
EE415 VLSI Design Writing into a Static Latch CLK CLK CLK D Q D CLK CLK D Converting into a MUX Forcing the state (can implement as NMOS-only) Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states
EE415 VLSI Design Reduced Clock Load Master-Slave Register D Q T 1 I 1 CLK CLK T 2 CLK CLK I 2 I 3 I 4
EE415 VLSI Design Avoid Clock Overlap CLK CLK A B (a) Schematic diagram (b) Overlapping clock pairs X D Q CLK CLK CLK CLK
EE415 VLSI Design Storage Mechanisms D CLK CLK Q Dynamic (charge-based) CLK CLK CLK D Q Static Very fast Was popular, now too risky
EE415 VLSI Design Making a Dynamic Latch Pseudo-Static D CLK CLK D Weak inverter
EE415 VLSI Design SR-Flip Flop Q S R Q S R Q Q 0 1 0 1 0 0 1 1 Q 1 0 0 Q 0 1 0 S R Q Q Q S R Q S R Q Q 1 0 1 0 1 1 0 0 Q 1 0 1 Q 0 1 1 Forbidden State Forbidden State S Q R Q
EE415 VLSI Design Cross-Coupled NOR M 1 M 2 M 3 M 4 Q M 5 S M 6 CLK M 7 R M 8 CLK V DD Q Cross-coupled NORs Added clock This is not used in datapaths any more, but is a basic building memory cell Transistors M5-M8 are wider to switch the state S Q R Q
EE415 VLSI Design Sizing Issues Output voltage dependence on transistor width Transient response For various W/L 5 and 6 4.0 3.5 3.0 W/L 5 and 6 (a) 2.5 2.0 0.0 0.5 1.0 1.5 2.0 Q (Volts) time (ns) (b) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1 2 W = 1 m 3 Volts Q S W = 0.9 m W = 0.8 m W = 0.7 m W = 0.6 m W = 0.5 m
EE415 VLSI Design Naming Conventions In our text: » a latch is level sensitive » a register is edge-triggered There are many different naming conventions » For instance, many books call edge- triggered elements flip-flops » This leads to confusion however
EE415 VLSI Design Latch versus Register Latch stores data when clock is low D Clk Q D Clk Q Register stores data when clock rises Clk Clk D D Q Q Falls with data Falls with clock
EE415 VLSI Design Latch-Based Design N latch is transparent when = 0 P latch is transparent when = 1 N Latch Logic Logic P Latch
EE415 VLSI Design Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair 1 0 D CLK Q M Master 0 1 CLK Q Slave Q M Q D