EDK - PowerPC Based Embedded Design in FPGA Using Xilinx...

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PowerPC Based Embedded Design in FPGA Using Xilinx EDK Department of Computer Science & Engineering
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About PowerPC 405 32-bit instruction/64-bit data Pipeline: 5-stage pipeline, mostly single cycle but for multiply(4cycles)/division(35 cycles) Memory addressing Support unaligned load/store Little endian operation Cache: 16K, 2-way cache, 32bytes block size Support for on-chip memory (OCM) With performance identical to a cache hit Buses: PLB, OPB, DCR,OCM
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PowerPC 405 Core Dedicated Hard IP Flexible Soft IP RocketIO PowerPC-based Embedded Design Full system customization to meet performance, functionality, and cost goals DCR Bus UART GPIO On-Chip Peripheral Hi-Speed Peripheral GB E-Net e.g. Memory Controller Arbiter On-Chip Peripheral Bus OPB Processor Local Bus Instruction Data PLB DSOCM BRAM ISOCM BRAM Off-Chip Memory ZBT SRAM DDR SDRAM SDRAM Bus Bridge IBM CoreConnect™ on-chip bus standard PLB, OPB, and DCR
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PPC Buses Processor Local Bus (PLB) One 32-bit address/three 64-bit data buses attached to the instruction-cache and data-cache units. Two of the 64-bit buses are attached to the data-cache unit, for read/write operations. The third 64-bit bus is attached to the instruction-cache unit to support instruction fetching. To provide a high-bandwidth, low-latency connection between bus agents that are the main producers and consumers of the bus transaction traffic . – connect your higher speed peripherals (e.g., G-Ethernet Mac) and memory. On-chip Peripheral Bus (OPB) Device Control Register (DCR) On-chip Memory Bus (OCM)
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PPC Buses Processor Local Bus (PLB) On-chip Peripheral Bus (OPB) A fully synchronous 32-bit address and 32-bit data bus. To provide a flexible connection path to peripherals and memory, while providing minimal performance impact to the PLB bus put slower peripherals on this bus, such as UARTs, GPIO, 10/100 E-Net MAC, etc. Device Control Register (DCR) On-chip Memory Bus (OCM)
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PPC Buses Processor Local Bus (PLB) On-chip Peripheral Bus (OPB) Device Control Register (DCR) A 32-bit bus for accessing device control registers Most traffic occurs during the system initialization period; however, some elements, such as the DMA controller and the interrupt controller cores, use the DCR bus to access normal functional registers used during operation.
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EDK - PowerPC Based Embedded Design in FPGA Using Xilinx...

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