interfacing - Software/hardware interfacing Department of...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Software/hardware interfacing Department of CSE University of South Carolina Interfacing Program I/O Interrupt I/O Direct Memory Access (DMA) Programming I/O Two types of instructions can support I/O: Memory-mapped load/store instructions. Requires no special instructions Assembly instructions (load/store) work with peripherals as well Special-purpose I/O instructions; No loss of memory addresses to peripherals Simpler address decoding logic in peripherals possible When number of peripherals much smaller than address space then high-order address bits can be ignored smaller and/or faster comparators Intel x86 provides in , out instructions. Most other CPUs use memory-mapped I/O. I/O instructions do not preclude memory-mapped I/O. memory-mapped I/O Define location for device: DEV1 EQU 0x1000; device I/O ports Read/write code: LDR r1,#DEV1 ; set up device adrs LDR r0,[r1] ; read DEV1 LDR r0,#8 ; set up value to write STR r0,[r1] ; write value to Peek and poke Traditional interfaces: int peek(char *location) { return *location; } void poke(char *location, char newval) { (*location) = newval; } Polling CPU constantly polls the device for its status while (TRUE) { /* read */ while (peek(IN_STATUS) == 0); achar = (char)peek(IN_DATA); /* write */ poke(OUT_DATA,achar); poke(OUT_STATUS,1); while (peek(OUT_STATUS) != 0); } Interrupt I/O Busy/wait is very inefficient. CPU cant do other work while testing device. Hard to do simultaneous I/O. Interrupts allow a device to request CPU attention when it needs. Interrupt CPU and call new subroutine to handle device Interrupt Service Routine (ISR) or Interrupt Service Handler. Generic interrupt mechanism intr? N Y Assume priority selection is handled before this point. N ignore Y ack vector? Y Y N timeout? Y bus error call table[vector] intr priority > current priority? continue execution Interrupt sequence CPU acknowledges request. Device sends vector. CPU calls handler. Software processes request....
View Full Document

Page1 / 31

interfacing - Software/hardware interfacing Department of...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online