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%20Organization%20and%20Design%20ARM%20edition.pdf Page 338 of 1074—page 500 of 1074 4.17 [10] <§4.5> What is the minimum number of cycles needed to completely execute n instructions on a CPU with a k stage pipeline? Justify your formula.
Stage cycle S1 S2 S3 S4 C1 C2 C3 C4 C5 C 4.18 - Note: The question is based on NO hardware Hazard Mitigation 4.18 [5] <§4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of registers X3 and X4 be? Fetch 1 Decode 1 Fetch 2 Execute 1 Decode 2 Fetch 3 Instruction 1 Completed Write back 1 Execute 2 Decode 3 Instruction 2 Completed Write back 2 Execute 3 Instruction 3 Completed Write back 3
Final value of x3 = 33 Final value of x4 = 26 4.19 - Note: The question is based on NO hardware Hazard Mitigation, but pay attention to when something is written to the register file and when it is read. 4.19 [10] <§4.5> Assume that X1 is initialized to 11 and X2 is initialized to 22. Suppose you executed the code below on a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the programmer is responsible for addressing data hazards by inserting NOP instructions where necessary). What would the final values of register X5 be? Assume the register file is written at the beginning of the cycle and read at the end of a cycle. Therefore, an ID stage will return the results of a WB state occurring during the same cycle. See Section 4.7 and Figure 4.51 for details ADDI X1, X2, #5 ADD X3, X1, X2 ADDI X4, X1, #15 ADD X5, X1, X1

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