Unformatted text preview: MSI Circuits Useful MSI circuits
▪ Four common and useful MSI circuits are:
❖
❖
❖
❖ Decoder
Demultiplexer
Encoder
Multiplexer ▪ Block-level outlines of MSI circuits:
code input decoder mux select entity data entity data encoder demux select code output Decoders
▪ Convert binary information from n input lines to
(max. of) 2n output lines. ▪ Known as n-to-m-line decoder, or simply n:m or
n×m decoder (m ≤ 2n). ▪ May be used to generate 2n (or fewer) minterms of
n input variables. Decoders
▪ Example: if codes 00, 01, 10, 11 are used to identify four
light bulbs, we may use a 2-bit decoder:
2-bit
code 2x4
F
X Dec F0
1 Y F2
F3 Bulb 0
Bulb 1
Bulb 2
Bulb 3 ▪ This is a 2×4 decoder which selects an output line based on
the 2-bit code supplied. ▪ Truth table: Decoders
▪ From truth table, circuit
for 2×4 decoder is: ▪ Note: Each output is a
2-variable minterm (X'Y',
X'Y, XY' or XY) F0 = X'Y'
F1 = X'Y
F2 = XY'
F3 = XY X Y Decoders
▪ Design a 3×8 decoder by yourself. Solution Decoders
▪ In general, for an n-bit code, a decoder could select up to
2n lines: n-bit
code : n to 2n
decoder : up to 2n
output lines As n input generates 2^n output, which reminds us of
canonical SOP, thus a decoder can be used to generate
any function Application of Decoder
• Example 1: Full adder circuit with decoder (3 x 8
decoder) Application of Decoder
• Example 2: BCD to Decimal
decoder: 4 input-10 output .
We can use don’t cares for
simplification. Demultiplexer
▪ Given an input line and a set of selection lines, the
demultiplexer will direct data from input to a selected
output line. ▪ An example of a 1-to-4 demultiplexer:
Outputs
Y0 = D.S1'.S0'
Data D demux Y1 = D.S1'.S0
Y2 = D.S1.S0'
Y3 = D.S1.S0 S1 S 0
select Demultiplexer • The demultiplexer is actually identical to a decoder
with enable. A decoder with an enable input can
function as a demultiplexer (or demux)
Decoder + enable= demultiplexer
• The selection of a specific output line is controlled
by the bit values of ‘n’-selection lines. S1
data demux output 2x4
Decoder S0 Y0 = D.S1'.S0'
Y1 = D.S1'.S0
Y2 = D.S1.S0' E
select
D Y3 = D.S1.S0 ve
i
t
c r
A
2-to-4-Line
s de Decoder with Enable input
a
n its
co constructed with NAND and Not gate
Note:
w
e
no e d
K
e: typ
t
No Low At a time only 1
output is low If enable ( E) is 0, circuit
works as decoder. 14 4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders with
enables 15 4-line-to-16 line Decoder constructed with two 3-line-to-8 line decoders with
enables • When w=0, the top decoder is enabled and the other is
disabled. The bottom decoder outputs are all 0’s , and
the top eight outputs generate min-terms 0000 to 0111.
• When w=1, the enable conditions are reversed. The
bottom decoder outputs generate min-terms 1000 to
1111, while the outputs of the top decoder are all 0’s. 16 F(a,b,c,d)=∑(0,1,3,5,12,13)
Implement the above boolean function using
a.
3:8 Decoder(s).
b.
2:4 Decoder(s). 17 F(a,b,c,d)=∑(0,1,3,5,12,13)
Implement the above boolean function using
a.
3:8 Decoder(s).
b.
2:4 Decoder(s). You have to connect D0,D1,D3,D5,D12
& D13 with OR Gate 18 HomeWork
• Design a BCD to 7 segment display using a 4x16 line decoder Multiplexer
▪ A multiplexer is a device which has
(i) a number of input lines
(ii) a number of selection lines
(iii) one output line ▪ A Multiplexer steers one of 2n inputs to a single output line,
using n selection lines. Also known as a data selector. inputs : 2n:1
Multiplexer
... select output Multiplexer
▪ Truth table for a 4-to-1 multiplexer: Inputs
I0
I1
I2
I3 0
4:1
1
MUX
Y
2
3
S1 S 0
select Output Inputs
I0
I1
I2
I3 mux S1 S 0
select Y Multiplexer
▪ Output of multiplexer is
“sum of the (product of data lines and
selection lines)”
▪Often known as Data selector as it selects one
of the many inputs and steers the binary
information to the output line. ▪ Example: the output of a 4-to-1 multiplexer is:
Y = I0.(S1’.S0') + I1.(S1’.S0) + I2.(S1.S0') + I3.(S1.S0) Try it yourself
• Draw the internal circuit diagram (logic diagram) of a 4-to-1
multiplexer. Solution
Y = I0.(S1’.S0') + I1.(S1’.S0) + I2.(S1.S0') + I3.(S1.S0) Larger Multiplexers
▪ Larger multiplexers can be constructed from smaller ones.
▪ An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (from two 4x1 and one 2x1): Larger Multiplexers
▪ Larger multiplexers can be constructed from smaller ones.
▪ An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (from two 4x1 and one 2x1):
I0
I1
I2
I3 4:1
MUX I0 2:1
MUX S1 S 0
I4
I5
I6
I7 4:1
MUX
S1 S 0 When
S2S1S0 = 000 I4 S2 I0 Y Larger Multiplexers
▪ Another implementation of an 8-to-1 multiplexer using
smaller multiplexers (four 2x1 and one 4x1): Larger Multiplexers
▪ Another implementation of an 8-to-1 multiplexer using
smaller multiplexers (four 2x1 and one 4x1):
I0
I1
I2
I3 2:1
MUX 2:1
MUX
I2 I0 S0
4:1
MUX S0
I4
I5 2:1 I4
MUX
S0 I6
I7 When
S2S1S0 = 000 I0 Y S2 S 1
2:1
MUX
S0 I6 Q: Can we use only 2:1 multiplexers? Larger Multiplexers
Q: Can we use only 2:1 multiplexers? Try it yourself: Larger Multiplexers
▪ A 16-to-1 multiplexer can be constructed from only 4-to-1 multiplexers: Multiplexer with enable input We can
construct it
using four 2x1
line multiplexer
for inserting the
input and then
three 2x1 line
multiplexer for
combining the
result Encoder
• Encoder is a digital function that produces a reverse operation of a
decoder!
• It has 2n input lines and n output lines Example: Octal-binary encoder Example: Octal-binary encoder There are 8 input variables so there will
28 input combination, amongst which in
Octal-binary encoder only 8 are useful Example: Priority Encoder
• Design a priority encoder, which will allow more than one input to
exist and encodes only the highest priority input line. For example,
8x3 encoder in a if user give D2 and D7 together, it will allow data of
D7 to pass. Priority Encoder
• Accepts multiple values and encodes them
• Works when more than one input is active • Consists of:
• Inputs (2n)
• Outputs • when more than one output is active, sets
output to correspond to highest input
• V (indicates whether any of the inputs are active).
This helps to show the output when all inputs are
0s
• Selectors / Enable Note: Amongst all 3
input, D2 is highest so
output reflects the
binary value of 2 D3 D2 D1 D0 A1 A0 V 0 0 0 0 x X 0 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 Note: V
is not
really an
output,
just
shows
whether
there is
an active
input or
not. Priority Encoder Priority Encoder Boolean Function
implementation using MSI Try it yourself
Using 4:1 MUX design
• AND gate
• OR gate
• NOT gate Solution
GND AND OR
GND
+5v +5v
NOT
+5v
GND X
X Try it yourself
a)Built the following function using 8x1 Mux.
F=∑(0,4,5)
b)Design same thing with 3x8 decoder
c) Try designing it with single 4x1 Mux Solution
• F=∑(0,4,5)
a) b) 5V Rules: for using smaller mux to build
larger equation Answer: Part ( c )
1
A
0
0 1 A 0 0 B C Built the following function using 4x1 Mux Try it yourself
a) Implement the below function using a 8x1 Mux.
b) Implement the below function using a 4x16 decoder and OR gates Solution Home-task: Try it yourself
Using 2:1 MUX design
• AND gate
• OR gate
• NOT gate Note:
• Both mux and decoder can be used to design combinational circuit.
• Decoder are mostly used to decoding binary information and mux are
mostly used to select path between multiple sources and a single
destination. 16 variables with 4x1 Mux F(a,b,c,d)=∑(0,1,4,5,9,14,15)
Implement the above boolean function using 4:1 MUX(s) and 2:1 MUX(s). Combining MSI to build
Combinational Design Circuit Exercise time!
• Design a BCD to Excess 3 code converter using ‘4x16’ decoder and
‘16x4’ encoder Solution 16:4
encoder Try it yourself
• Design a full adder using ‘3x8’ decoder and ‘4x2’ encoder Solution: Try it yourself
• Design ‘4x1’ mux using ‘2x4’ decoder
• Design ‘4x1’ demux using ‘2x4’ decoder ...
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