Unformatted text preview: Chapter 10 Combinational
Circuits Figure 10.1 Combinational circuit
• The output depends only on the input Figure 10.2 Methods to describe a
combinational circuit
• Truth table
• Boolean algebraic expression
• Logic diagram Truth table
• Lists the output for every combination of
the input Figure 10.3 a b c x y 0
0
0
0
1
1
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1 0
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1
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1 0
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1 0
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0 0
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0 Figure 10.4 a b c d x y 0
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0 Boolean algebra
• Three basic operations
‣ Binary OR +
‣ Binary AND •
‣ Unary Complement ´ Ten properties of
boolean algebra
• Commutative
• Associative
• Distributive
• Identity
• Complement Commutative
C OMPUTER S YSTEMS C HAPTER 10
x+y =y+x
x·y =y·x (x + y) + z = x + (y + z)
(x · y) · z = x · (y · z) x + (y · z) = (x + y) · (x + z) C OMPUTER S YSTEMS C HAPTER 10 Associative
x+y =y+x
x·y =y·x (x + y) + z = x + (y + z)
(x · y) · z = x · (y · z) x + (y · z) = (x + y) · (x + z)
x · (y + z) = (x · y) + (x · z)
x+0=x x+y =y+x
x·y =y·x (x + y)Distributive
+ z = x + (y + z)
(x · y) · z = x · (y · z) x + (y · z) = (x + y) · (x + z)
x · (y + z) = (x · y) + (x · z)
x+0=x
x·1=x x + (x ) = 1
(x + y) + z = x + (y + z)
(x · y) · z = x · (y · z) x + Identity + y) · (x + z)
(y · z) = (x
x · (y + z) = (x · y) + (x · z)
x+0=x
x·1=x x + (x ) = 1
x · (x ) = 0
x + (y · z) = (x + y) · (x + z)
x · (y + z) = (x · y) + (x · z) Complement
x+0=x
x·1=x x + (x ) = 1
x · (x ) = 0
x + y · z = (x + y) · (x + z) x · (y + z) = x · y + x · z Figure 10.5 Precedence Operator Highest Complement
AND
OR Lowest x·1=x x + (x ) = 1
Distributive
x · (x ) = 0 x + y · z = (x + y) · (x + z) x · (y + z) = x · y + x · z
x+x =1
x·x =0
x · (x ) = 0
Complementy) · (x + z)
x + y · z = (x +
x · (y + z) = x · y + x · z
x+x =1
x·x =0
(x + y) + z
x+y+z x · (y + z) = x · y + x · z
x+x =1
Associativity
x·x =0
(x + y) + z
x+y+z
x+x=x
x·x=x Duality
• To obtain the dual expression
‣ Exchange + and •
‣ Exchange 1 and 0 (x + y) + z
Idempotentz property
x+y+
x+x=x
x·x=x
x+1=1
x·0=0 x+x·y =x x+y+z Zero+ x = x
theorem
x
x·x=x x+1=1
x·0=0 x+x·y =x x · (x + y) = x x·y+x ·z+y·z =x·y+x ·z
x+x=x
x·x=x Absorption 1property
x+ =1
x·0=0 x+x·y =x x · (x + y) = x x·y+x ·z+y·z =x·y+x ·z
(x + y) · (x + z) · (y + z) = (x + y) · (x + z)
x+1=1
x·0=0 Consensus· ytheorem
x+x
=x
x · (x + y) = x x·y+x ·z+y·z =x·y+x ·z
(x + y) · (x + z) · (y + z) = (x + y) · (x + z)
(a · b ) = a + b
(a + b) = a · b
x · (x + y) = x x·y+x ·z+y·z =x·y+x ·z
De ·Morgan’s + y) · (x + z)
law
x + y) · (x + z) (y + z) = (x
(a · b) = a + b
(a + b) = a · b
(x ) = x
1 =0
0 =1
(a · b ) = a + b
Complement theorems
(a + b) = a · b
(x ) = x
1 =0
0 =1
1 Logic diagrams
• An interconnection of logic gates
• Closely resembles the hardware
‣ Gate symbol represents a group of
transistors and other electronic
components
‣ Lines connecting gate symbols represent
wires Figure 10.6 a a
x x b b x= a . b x =a+ b a a b x a b x 0
0
1
1 0
1
0
1 0
0
0
1 0
0
1
1 0
1
0
1 0
1
1
1 (a) AND gate. (b) OR gate. x x = aЈ
a x 0
1 1
0 (c) Inverter. Figure 10.7 a a a x x x
b b b x = (a . b)Ј x = (a + b)Ј x=ab a b x a b x a b x 0
0
1
1 0
1
0
1 1
1
1
0 0
0
1
1 0
1
0
1 1
0
0
0 0
0
1
1 0
1
0
1 0
1
1
0 (a) NAND gate. (b) NOR gate. (c) XOR gate. Figure 10.8 a a
x b x
b (a) AND inverter. (b) NAND. Figure 10.9 Precedence Operator Highest Complement
AND
XOR
OR Lowest Figure 10.10 a a
b
c
x=aиbиc x b c x 0
0
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1 0
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1 Set theory
representation
• OR gate is set union
• AND gate is set intersection
• Inverter is set complement Figure 10.11 x x y x y (a) x (b) x · y x y
(c) x + x · y Figure 10.12 1 Truth table Onetoone
correspondence Boolean expression Boolean expression Boolean expression Logic diagram Logic diagram Logic diagram This section describes the correspondence among the three representations of a
combinational circuit. Boolean expressions and
logic diagrams
• AND gate corresponds to AND operation
• OR gate corresponds to OR operation
• Inverter corresponds to complement
operation Figure 10.13 a
b
c bЈ
bЈc a+b c
a + b .· cЈ Figure 10.14 a ab (ab + bcЈ ) a b ab + bcЈ
b
bcЈ c a cЈ ((ab + bcЈ ) a)Ј Abbreviated logic
diagrams
• Any signal can be duplicated by a junction of
two wires • The complement of any variable can be
produced by an inverter Figure 10.15 a
b
b
cЈ a Figure 10.16 2 (a bc ⊕ c + a + d)
aЈ
b
c a
d
c Truth tables and boolean
expressions
• Given a truth table, write a boolean expression without parentheses as an OR of
several AND terms • Each AND term corresponds to a 1 in the
truth table Figure 10.17 a b c x 0
0
0
0
1
1
1
1 0
0
1
1
0
0
1
1 0
1
0
1
0
1
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1 1
1
1
0
1
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1 Figure 10.18 a b c d x 0
0
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0 0
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1 0
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0 Twolevel circuits
• The gate delay is the time is the time it takes
for the output of a gate to respond to a
change in its input • Any combinational circuit can be transformed into an ANDOR circuit or an
ORAND circuit with at most two gate
delays (not counting the gate delay of any
inverters) Figure +
(a bc ⊕ c10.19 a + aЈ
b
dЈ aЈ
cЈ
dЈ a bd + a c d
(a + b + c )(a
a bd + a c d Figure 10.20 (a + b + c )(a + b + c)
a
bЈ
cЈ
aЈ
bЈ
c ANDOR versus
ORAND
• To transform any expression x to an
equivalent ORAND expression ‣ Transform the complement of x to an
ANDOR expression without parentheses
using boolean algebra theorems
‣ Use x = (x´)´ and De Morgan’s law Figure 10.21
(a + b + c )(a + b + c) (abc) = a + b + c (abc) = a + b + c (a + b + c) = a b c abc + def = [(abc) (def ) ]
a a
abc + def = [(abc) (def ) ] b
c b
c a
b
c a
b
c (a) A NAND gate as an inverted
input OR gate. (b) A NOR gate as an inverted
input AND gate. Figure 10.22 abc + def = [(abc) (def ) ] (a + b= a += a bcc
+ c) b +
(abc)
abc + + c)= [(abc) (def ) ]
(a + b def = a b c
(a ·+ def = [(abc) (def ) ]
a) = a
abc
(a· + a= = a
(a a) ) a
(a + b = a=
(a + a)+ c) [(a + b + c)(d + e + f )]
(a + b + c) = [(a + b + c)(d + e + f )] Figure 10.23 (a + a) = a Figure 10.24 (a + b + c)(d + e + f ) = [(a + b + c) + (d + e + f ) ] Canonical expressions
• A minterm is a term in an ANDOR expression in which all input variables occur
exactly once • A canonical expression is an OR of minterms
in which no two identical minterms appear • A canonical expression is directly related to
a truth table because each minterm in the
expression represents a 1 in the truth table (a + a) = a Figure 10.25 (a + b + c)(d + e + f ) =
x(a, b, c) = Σ(3, 6, 7) (a + b + c)(d + e + f ) = [(
Figure 10.25 x(a, b, c) = Σ(3, 6, 7)
x(a, b, c) = Π(0, 1, 2, 4, 5) Karnaugh maps
• The distance between two minterms is the
number of places in which they differ • Two minterms are adjacent if the distance
between them is one • A Karnaugh map is a truth table arranged so
that adjacent cells represent adjacent
minterms Figure 10.26 Figure 10.27
x(a, b, c) = Π(0, 1, 2, 4, 5) x(a, b, c) = a bc + a x(a, b, c) = a bc + a bc x(a, b, c) = a b x(a, b, c) = a b Figure 10.28 x(a, b, c) = a b 30) x(a, b, c) = ab c + abc 31) = ac x(a, b, c) = Π(0, 1, 2, 4, 5) Figure 10.29 x(a, b, c) = a bc + a bc
x(a, b, c) = a b (30) x(a, b, c) = ab c + abc (31) = ac (32) x(a, b, c) = a bc + abc + abc (33) = bc + ab Figure 10.30 x(a, b, c) = a b Figure 10.31 (30) x(a, b, c) = ab c + abc (31) = ac (32) x(a, b, c) = a bc + abc + abc (33) = bc + ab (34) x(a, b, c) = Σ(0, 1, 5, 7) (35) = a b + ac x(a, b, c) = Σ(0, 1, 5, 7)
(36)
(37) = a b + ac
x(a, (38) = Σ(0, 2, 4, 6, 7)
b, c)
= b c + bc + ab
(39)
x(a, b, c) = Σ(0, 2, 4, 6, 7)
= c + ab x(a, b, c) = Σ(0, 2, 4, 6, 7)
Figure 10.32
= b c + bc + ab
x(a, b, c) = Σ(0, 2, 4, 6, 7)
= c + ab Figure 10.33 Figure 10.34 x(a, b, c, d) = c d + b d x(a, b, c) = c d + b d
x(a, b, c, d) = a c d + b c + b d Figure 10.35 x(a, b, c) = c d + b d x(a, b, c, d) = a c d Figure 10.36+ b d
+ b c
x(a, b, c, d) = a c d + b c + b d
x(a, b, c, d) = c d + bcd + abc
x(a, b, c, d) = c d + bcd + abc
x(a, b, c, d) = c d + bcd + abd
x(a, b, c, d) = c d + bcd + abd x(a, b, c, d) = c d + bcd + abc x(a, b, c, d) = c d + bcd +
Figure 10.37 x(a, b, c, d) = c d + bcd + abd ac + a c + c d + a b + b ac + a c + c d + a b + bcd ac + a d + a b + bcd ac + a d + a b + bcd ac + a d + a b + bcd
a c + b c + c d + abd Figure 10.38 Dual Karnaugh maps
• To minimize a function in an ORAND expression minimize the complement of the
function in the ANDOR expression • Use x = (x´)´ and De Morgan’s law x(a, b, c, d) = c d + bcd + abd
x(a, b, c, d) = c d + bcd + abc Figure 10.29(c), 10.39 ac + a c + cd + a b + bcd
x(a, b, c, d) = c d + bcd + abd
ac + a d + a b + bcd ac + a c + c d + a b + bcd
a c + b c + c d + abd ac + a d + a b + bcd
x = bc + ab a c + b c + c d + abd
(40)
x = bc + ab x = b + a c (41) x = (x ) (42) (40)
(43)
(41) = (b + a c ) x = b(a +ac)
b + c
=
x = (x ) Don’tcare conditions
• If an input combination is never expected to
be present, you can choose to make it 0 or
1, whichever will better minimize the circuit • A don’t care condition is shown as an X in a
Karnaugh map = (b + a c ) Figure 10.40
= bc + ac (45) = b(a + c) (46)
x(a, b, c) = Σ(2, 4, 6)
(47) = bc + ac x(a, b, c) = Σ(2, 4, 6) + d(0, 7)
= c x(a, b, c) = Σ(2, 4, 6) + d(0, 7)
= c Enable lines
• An enable line to a combinational device
turns the device on or off ‣ If enable = 0 the output is 0 regardless of
any other inputs
‣ If enable = 1 the device performs its
function with the output depending on the
other inputs Figure 10.41 Figure 10.42 Multiplexer
• A multiplexer selects one of several data inputs to be routed to a single data output • Control lines determine the particular data
input to be passed through Figure 10.43 Figure 10.44 Binary decoder
• A decoder takes a binary number as input
and sets one of the data output lines to 1
and the rest to 0 • The data line that is set to 1 depends on the
value of the binary number that is input Figure 10.45 Figure 10.46 Figure 10.47 Demultiplexer
• A demultiplexer routes a single input value
to one of several output lines • Control lines determine the data output line
to which the input gets routed Figure 10.48 Half adder
• The half adder adds the rightmost two bits
of a binary number • Inputs: The two bits
• Outputs: The sum bit and the carry bit Figure 10.49 Full adder
• The full adder adds one column of a binary
number • Inputs: The two bits for that column and the
carry bit from the previous column • Outputs: The sum bit and the carry bit for
the next column Figure 10.50 Figure 10.51 Ripplecarry adder
• The ripplecarry adder adds two nbit binary
numbers • Inputs: The two nbit binary numbers to be
added • Outputs: The nbit sum, the C bit for the
carry out, and the V bit for signed integer
overﬂow Figure 10.52 Computing the V bit
• You can only get an overﬂow in one of two
cases ‣ A and B are both positive, and the result is
negative
‣ A and B are both negative, and the result is
positive Adder/subtracter
• Based on the relation
NEG x = 1 + NOT x • XOR gates act as selective inverters
• A – B = A + (–B) Figure 10.53 Arithmetic Logic Unit
(ALU)
• Performs 16 different functions
• Inputs: Two nbit binary numbers, four control lines that determine which function
will be executed, and one carry input line • Outputs: The nbit result, the NZVC bits Figure 10.54 Figure 10.55
ALU control
(dec)
(bin)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 Result N Status bits
Zout
V A
A plus B
A plus B plus Cin
A plus B plus 1
A plus B plus Cin
AиB
AиB
A+B
A+B
AB
A
ASL A
ROL A
ASR A
ROR A
0 N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
A<4> Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
A<5> 0
V
V
V
V
0
0
0
0
0
0
V
0
0
0
A<6> Cout
0
C
C
C
C
0
0
0
0
0
0
C
C
C
C
A<7> Figure 10.56 A B Cin Computation
Unit VC Result 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 4 × 16
Decoder 0 0 0 0 0 0 0 0 Result ALU Result N ZV C NZ VC 12 TwoInput Multiplexers
Result N Zout 15
V Cout The multiplexer of
Figure 10.56
• If line 15 is 1, Result and NZVC from the left
are routed to the output • If line 15 is 0, Result and NZVC from the
right are routed to the output A Figure 10.57 B
8 8 Cin
A A A Unit
Result V C B A Cin Result V C A Logic Unit 5
A AND B Arithmetic Unit
E B d e f g Result V C Cin Logic Unit 14
ROR A
E Result V C E
0
1
2
3
4
5 8 8 8 10 12Input OR Gates
8
Result V C 8 14 Figure 10.58
A Unit A E
0 V
Result 0 C Figure 10.59
Arithmetic Unit B7 A7 B0 A0 B6 A6 Sub C
B A
Cout
S C Cin B A
Cout B A Cout Cin Cin S S V
Result Cin
d
e
f
g Figure 10.60(a) A<high> B<high> A plus B plus Cin
Cout
Cin A<low> B<low> A plus B
Cout S<high> S<low>
(a) 16bit addition. w> Figure 10.60(b) A<high> B<high> A plus B plus Cin
Cout
Cin A<low> B<low> A plus B +1
Cout D<high>
(b) 16bit subtraction. D<low> Figure 10.61 Function d e f g Sub C A plus B
A plus B plus Cin
A plus B plus 1
A plus B plus Cin 1
0
0
0 0
1
0
0 0
0
1
0 0
0
0
1 0
0
1
1 0
Cin
1
Cin Figure 10.62 a a b b (a) (b) a
b
c (c) Figure 10.63 (a) (b) (c) (d) Figure 10.64 s=1 s=0
a x a x b y b y s s Figure 10.65 s1 s0 = 01 s1 s0 = 00 s1 s0 = 10 s1 s0 = 11 a x a x a x a x b y b y b y b y s1 s0 s1 s0 s1 s0 s1 s0 ...
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 Logic gate

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